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Searched refs:CDCE706_PLL_FREQ_MAX (Results 1 – 1 of 1) sorted by relevance

/drivers/clk/
Dclk-cdce706.c47 #define CDCE706_PLL_FREQ_MAX 300000000 macro
314 div <= CDCE706_PLL_FREQ_MAX / rate; ++div) { in cdce706_divider_round_rate()