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Searched refs:CE_PARTITION_BASE (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dsi_enums.h136 #define CE_PARTITION_BASE 3 macro
Dnvd.h58 #define CE_PARTITION_BASE 3 macro
Dsoc15d.h83 #define CE_PARTITION_BASE 3 macro
Dvid.h117 #define CE_PARTITION_BASE 3 macro
Dcikd.h235 #define CE_PARTITION_BASE 3 macro
Dsid.h1669 #define CE_PARTITION_BASE 3 macro
Dgfx_v6_0.c2046 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in gfx_v6_0_cp_gfx_start()
Dgfx_v7_0.c2545 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in gfx_v7_0_cp_gfx_start()
Dgfx_v10_0.c2754 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in gfx_v10_0_cp_gfx_start()
Dgfx_v9_0.c3182 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in gfx_v9_0_cp_gfx_start()
Dgfx_v8_0.c4249 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in gfx_v8_0_cp_gfx_start()
/drivers/gpu/drm/radeon/
Dsid.h1606 #define CE_PARTITION_BASE 3 macro
Dcikd.h1701 #define CE_PARTITION_BASE 3 macro
Dsi.c3582 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in si_cp_start()
Dcik.c4005 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in cik_cp_gfx_start()