Searched refs:CG_DISPLAY_GAP_CNTL (Results 1 – 13 of 13) sorted by relevance
| /drivers/gpu/drm/radeon/ |
| D | rv6xxd.h | 130 #define CG_DISPLAY_GAP_CNTL 0x7dc macro
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| D | cypress_dpm.c | 1731 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); in cypress_enable_display_gap()
1740 WREG32(CG_DISPLAY_GAP_CNTL, tmp); in cypress_enable_display_gap()
1748 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); in cypress_program_display_gap()
1759 WREG32(CG_DISPLAY_GAP_CNTL, tmp); in cypress_program_display_gap()
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| D | rv770_dpm.c | 879 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); in rv770_enable_display_gap()
884 WREG32(CG_DISPLAY_GAP_CNTL, tmp); in rv770_enable_display_gap()
1343 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); in rv770_program_display_gap()
1356 WREG32(CG_DISPLAY_GAP_CNTL, tmp); in rv770_program_display_gap()
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| D | rv6xx_dpm.c | 989 WREG32(CG_DISPLAY_GAP_CNTL, tmp); in rv6xx_enable_display_gap()
1182 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); in rv6xx_program_display_gap()
1195 WREG32(CG_DISPLAY_GAP_CNTL, tmp); in rv6xx_program_display_gap()
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| D | rv770d.h | 255 #define CG_DISPLAY_GAP_CNTL 0x714 macro
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| D | sid.h | 301 #define CG_DISPLAY_GAP_CNTL 0x828 macro
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| D | cikd.h | 129 #define CG_DISPLAY_GAP_CNTL 0xC0200060 macro
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| D | si_dpm.c | 3687 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); in si_program_display_gap()
3698 WREG32(CG_DISPLAY_GAP_CNTL, tmp); in si_program_display_gap()
3801 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); in si_enable_display_gap()
3810 WREG32(CG_DISPLAY_GAP_CNTL, tmp); in si_enable_display_gap()
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| D | ci_dpm.c | 1987 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); in ci_program_display_gap()
1999 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); in ci_program_display_gap()
2048 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); in ci_enable_display_gap()
2054 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); in ci_enable_display_gap()
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| D | evergreend.h | 193 #define CG_DISPLAY_GAP_CNTL 0x714 macro
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | sid.h | 303 #define CG_DISPLAY_GAP_CNTL 0x20a macro
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| D | si_dpm.c | 4152 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); in si_program_display_gap()
4163 WREG32(CG_DISPLAY_GAP_CNTL, tmp); in si_program_display_gap()
4266 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); in si_enable_display_gap()
4275 WREG32(CG_DISPLAY_GAP_CNTL, tmp); in si_enable_display_gap()
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| /drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | smu7_hwmgr.c | 391 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, in smu7_enable_display_gap()
394 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, in smu7_enable_display_gap()
4070 …display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->nu… in smu7_program_display_gap()
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