Searched refs:CP_RB0_CNTL (Results 1 – 10 of 10) sorted by relevance
| /drivers/gpu/drm/radeon/ |
| D | nid.h | 484 #define CP_RB0_CNTL 0xC104 macro
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| D | sid.h | 1246 #define CP_RB0_CNTL 0xC104 macro
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| D | cikd.h | 1302 #define CP_RB0_CNTL 0xC104 macro
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| D | si.c | 3674 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3677 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3693 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
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| D | ni.c | 1632 CP_RB0_CNTL, in cayman_cp_resume()
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| D | cik.c | 4088 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4091 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in cik_cp_gfx_resume()
4106 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v8_0.c | 4307 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v8_0_cp_gfx_resume()
4308 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v8_0_cp_gfx_resume()
4309 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3); in gfx_v8_0_cp_gfx_resume()
4310 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1); in gfx_v8_0_cp_gfx_resume()
4312 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v8_0_cp_gfx_resume()
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| D | sid.h | 1275 #define CP_RB0_CNTL 0x3041 macro
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| D | gfx_v10_0.c | 2832 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume()
2833 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
2835 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v10_0_cp_gfx_resume()
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| D | gfx_v9_0.c | 3213 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v9_0_cp_gfx_resume()
3214 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v9_0_cp_gfx_resume()
3216 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v9_0_cp_gfx_resume()
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