| /drivers/scsi/aacraid/ |
| D | aacraid.h | 1080 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
1081 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
1082 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR)) argument
1083 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR)) argument
1142 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR)) argument
1143 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR)) argument
1144 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR)) argument
1145 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR)) argument
1160 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR)) argument
1161 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR)) argument
[all …]
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| /drivers/dma/ |
| D | txx9dmac.c | 296 channel64_readl(dc, CSR)); in txx9dmac_dump_regs()
308 channel32_readl(dc, CSR)); in txx9dmac_dump_regs()
339 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { in txx9dmac_dostart()
349 channel64_writel(dc, CSR, 0xffffffff); in txx9dmac_dostart()
370 channel32_writel(dc, CSR, 0xffffffff); in txx9dmac_dostart()
480 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); in txx9dmac_dump_desc()
493 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
519 channel_writel(dc, CSR, errors); in txx9dmac_handle_error()
545 csr = channel64_readl(dc, CSR); in txx9dmac_scan_descriptors()
546 channel64_writel(dc, CSR, csr); in txx9dmac_scan_descriptors()
[all …]
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| D | txx9dmac.h | 78 TXX9_DMA_REG32(CSR); /* Channel Status Register */
88 u32 CSR; member
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| D | Kconfig | 481 tristate "CSR SiRFprimaII/SiRFmarco DMA support"
485 Enable support for the CSR SiRFprimaII DMA engine.
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| /drivers/staging/qlge/ |
| D | qlge_mpi.c | 9 tmp = ql_read32(qdev, CSR); in ql_unpause_mpi_risc()
13 ql_write32(qdev, CSR, CSR_CMD_CLR_PAUSE); in ql_unpause_mpi_risc()
23 ql_write32(qdev, CSR, CSR_CMD_SET_PAUSE); in ql_pause_mpi_risc()
25 tmp = ql_read32(qdev, CSR); in ql_pause_mpi_risc()
40 ql_write32(qdev, CSR, CSR_CMD_SET_RST); in ql_hard_reset_mpi_risc()
42 tmp = ql_read32(qdev, CSR); in ql_hard_reset_mpi_risc()
44 ql_write32(qdev, CSR, CSR_CMD_CLR_RST); in ql_hard_reset_mpi_risc()
175 if (ql_read32(qdev, CSR) & CSR_HRI) in ql_exec_mb_cmd()
194 ql_write32(qdev, CSR, CSR_CMD_SET_H2R_INT); in ql_exec_mb_cmd()
516 ql_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT); in ql_mpi_handler()
[all …]
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| D | qlge.h | 803 CSR = 0x14, enumerator
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| D | qlge_dbg.c | 1471 DUMP_REG(qdev, CSR); in ql_dump_regs()
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| /drivers/dma/ti/ |
| D | omap-dma.c | 364 omap_dma_chan_read(c, CSR); in omap_dma_clear_csr()
366 omap_dma_chan_write(c, CSR, ~0); in omap_dma_clear_csr()
371 unsigned val = omap_dma_chan_read(c, CSR); in omap_dma_get_csr()
374 omap_dma_chan_write(c, CSR, val); in omap_dma_get_csr()
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| /drivers/misc/eeprom/ |
| D | Kconfig | 112 tristate "IDT 89HPESx PCIe-swtiches EEPROM / CSR support"
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| /drivers/net/ethernet/renesas/ |
| D | ravb.h | 52 CSR = 0x000C, enumerator
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| D | ravb_main.c | 78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); in ravb_config()
671 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, in ravb_stop_dma()
680 error = ravb_wait(ndev, CSR, CSR_RPO, 0); in ravb_stop_dma()
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| /drivers/spi/ |
| D | spi-at91-usart.c | 294 aus->status = at91_usart_spi_readl(aus, CSR); in at91_usart_spi_read_status()
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| D | Kconfig | 671 tristate "CSR SiRFprimaII SPI controller"
675 SPI driver for CSR SiRFprimaII SoCs
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| /drivers/pinctrl/ |
| D | Kconfig | 239 bool "CSR SiRFprimaII pin controller driver"
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| /drivers/mmc/host/ |
| D | Kconfig | 289 tristate "SDHCI support on CSR SiRFprimaII and SiRFmarco SoCs"
878 the Cypress Astoria chip with firmware compliant with CSR's
881 CSR boards with this device include: USB<>SDIO (M1985v2),
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| /drivers/bluetooth/ |
| D | Kconfig | 140 USB Bluetooth devices based on CSR BlueCore chip, including PCMCIA and
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| /drivers/i2c/busses/ |
| D | Kconfig | 971 tristate "CSR SiRFprimaII I2C interface"
975 CSR SiRFprimaII I2C interface.
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| /drivers/input/misc/ |
| D | Kconfig | 795 tristate "CSR SiRFSoC power on/off/suspend key support"
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| /drivers/tty/serial/ |
| D | Kconfig | 294 Support for the on-chip UART on the CSR SiRFprimaII series,
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| /drivers/watchdog/ |
| D | Kconfig | 781 Support for CSR SiRFprimaII and SiRFatlasVI watchdog. When
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