| /drivers/pinctrl/aspeed/ |
| D | pinctrl-aspeed-g5.c | 1298 #define D2 174 macro
1299 SIG_EXPR_LIST_DECL_SINGLE(D2, GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22));
1300 SIG_EXPR_LIST_DECL_SINGLE(D2, RMII2CRSDV, RMII2, RMII2_DESC);
1301 SIG_EXPR_LIST_DECL_SINGLE(D2, RGMII2RXD2, RGMII2);
1302 PIN_DECL_(D2, SIG_EXPR_LIST_PTR(D2, GPIOV6), SIG_EXPR_LIST_PTR(D2, RMII2CRSDV),
1303 SIG_EXPR_LIST_PTR(D2, RGMII2RXD2));
1312 FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
1313 FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6);
1984 ASPEED_PINCTRL_PIN(D2),
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| D | pinctrl-aspeed-g6.c | 1391 #define D2 226 macro
1392 SIG_EXPR_LIST_DECL_SESG(D2, RGMII2RXCK, RGMII2, SIG_DESC_SET(SCU400, 18),
1394 SIG_EXPR_LIST_DECL_SESG(D2, RMII2RCLKI, RMII2, SIG_DESC_SET(SCU400, 18),
1396 PIN_DECL_2(D2, GPIO18C2, RGMII2RXCK, RMII2RCLKI);
1431 FUNC_GROUP_DECL(RGMII2, D4, C2, C1, D3, E4, F5, D2, E3, D1, F4, E2, E1);
1432 FUNC_GROUP_DECL(RMII2, D4, C2, C1, D3, D2, D1, F4, E2, E1);
1688 ASPEED_PINCTRL_PIN(D2),
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| D | pinctrl-aspeed-g4.c | 645 #define D2 81 macro
646 SIG_EXPR_LIST_DECL_SINGLE(D2, SDA5, I2C5, I2C5_DESC);
647 PIN_DECL_1(D2, GPIOK1, SDA5);
649 FUNC_GROUP_DECL(I2C5, E3, D2);
1996 ASPEED_PINCTRL_PIN(D2),
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| /drivers/memory/tegra/ |
| D | tegra114.c | 960 TEGRA114_MC_RESET(3D2, 0x200, 0x204, 13),
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| D | tegra30.c | 983 TEGRA30_MC_RESET(3D2, 0x200, 0x204, 13),
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| /drivers/pinctrl/sh-pfc/ |
| D | pfc-r8a77970.c | 196 #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F…
572 PINMUX_IPSR_GPSR(IP5_15_12, D2),
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| D | pfc-r8a77980.c | 229 #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F…
649 PINMUX_IPSR_GPSR(IP5_15_12, D2),
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| D | pfc-r8a77990.c | 83 #define GPSR0_2 F_(D2, IP5_31_28)
263 #define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4…
846 PINMUX_IPSR_GPSR(IP5_31_28, D2),
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| D | pfc-sh7734.c | 726 PINMUX_IPSR_GPSR(IP1_28_26, D2),
1414 GPIO_FN(D2), GPIO_FN(SD0_DAT2_A), GPIO_FN(MMC_D2_A),
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| D | pfc-r8a7795-es1.c | 95 #define GPSR0_2 F_(D2, IP5_23_20)
301 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, …
932 PINMUX_IPSR_GPSR(IP5_23_20, D2),
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| D | pfc-r8a7795.c | 95 #define GPSR0_2 F_(D2, IP5_23_20)
302 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, …
939 PINMUX_IPSR_GPSR(IP5_23_20, D2),
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| D | pfc-r8a77965.c | 100 #define GPSR0_2 F_(D2, IP5_23_20)
307 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, …
945 PINMUX_IPSR_GPSR(IP5_23_20, D2),
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| D | pfc-r8a7796.c | 99 #define GPSR0_2 F_(D2, IP5_23_20)
306 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, …
942 PINMUX_IPSR_GPSR(IP5_23_20, D2),
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| D | pfc-r8a7792.c | 349 PINMUX_SINGLE(D2),
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| D | pfc-sh7264.c | 1303 GPIO_FN(D2),
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| D | pfc-r8a73a4.c | 360 F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
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| D | pfc-sh7757.c | 1662 GPIO_FN(D2),
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| D | pfc-sh7724.c | 1407 GPIO_FN(D2),
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| D | pfc-r8a77470.c | 583 PINMUX_IPSR_GPSR(IP1_19_16, D2),
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| D | pfc-sh7269.c | 1725 GPIO_FN(D2),
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| D | pfc-r8a7778.c | 690 PINMUX_IPSR_NOGP(IP2_20, D2),
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| D | pfc-r8a7794.c | 733 PINMUX_IPSR_GPSR(IP0_25, D2),
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| D | pfc-r8a7791.c | 813 PINMUX_IPSR_GPSR(IP0_2, D2),
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| D | pfc-r8a7790.c | 812 PINMUX_IPSR_GPSR(IP0_8_6, D2),
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| /drivers/pinctrl/ |
| D | pinctrl-pic32.c | 925 PIC32_PINCTRL_GROUP(50, D2,
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