Searched refs:DF (Results 1 – 5 of 5) sorted by relevance
| /drivers/gpu/drm/amd/amdgpu/ |
| D | df_v1_7.c | 42 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); in df_v1_7_enable_broadcast_mode()
44 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp); in df_v1_7_enable_broadcast_mode()
46 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, in df_v1_7_enable_broadcast_mode()
54 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); in df_v1_7_get_fb_channel_number()
79 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
82 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp); in df_v1_7_update_medium_grain_clock_gating()
84 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
87 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp); in df_v1_7_update_medium_grain_clock_gating()
100 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_get_clockgating_state()
108 WREG32_FIELD15(DF, 0, DF_CS_AON0_CoherentSlaveModeCtrlA0, in df_v1_7_enable_ecc_force_par_wr_rmw()
|
| D | df_v3_6.c | 229 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); in df_v3_6_enable_broadcast_mode()
231 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp); in df_v3_6_enable_broadcast_mode()
233 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, in df_v3_6_enable_broadcast_mode()
241 tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0); in df_v3_6_get_fb_channel_number()
269 tmp = RREG32_SOC15(DF, 0, in df_v3_6_update_medium_grain_clock_gating()
273 WREG32_SOC15(DF, 0, in df_v3_6_update_medium_grain_clock_gating()
276 tmp = RREG32_SOC15(DF, 0, in df_v3_6_update_medium_grain_clock_gating()
280 WREG32_SOC15(DF, 0, in df_v3_6_update_medium_grain_clock_gating()
295 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v3_6_get_clockgating_state()
|
| /drivers/scsi/ |
| D | aha1542.h | 15 #define DF BIT(2) /* Data In Port Full */ macro
18 #define STATMASK (STST | DIAGF | INIT | IDLE | CDF | DF | INVDCMD)
|
| D | aha1542.c | 128 if (!wait_mask(STATUS(base), DF, DF, 0, timeout)) in aha1542_in()
212 if (!wait_mask(STATUS(sh->io_port), STATMASK, INIT | IDLE, STST | DIAGF | INVDCMD | DF | CDF, 0)) in aha1542_test_port()
225 if (!wait_mask(STATUS(sh->io_port), DF, DF, 0, 0)) in aha1542_test_port()
231 if (inb(STATUS(sh->io_port)) & DF) in aha1542_test_port()
546 if (i & DF) { in aha1542_getconfig()
647 if (i & DF) { in aha1542_query()
927 STATMASK, IDLE, STST | DIAGF | INVDCMD | DF | CDF, 0)) { in aha1542_reset()
|
| /drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | vega10_hwmgr.c | 931 data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) & in vega10_hwmgr_backend_init()
|