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Searched refs:DMA_CNTL (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dsi_dma.c172 dma_cntl = RREG32(DMA_CNTL + sdma_offsets[i]); in si_dma_start()
174 WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl); in si_dma_start()
597 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
599 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
602 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
604 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
613 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
615 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
618 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
620 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
Dsid.h1897 #define DMA_CNTL 0x340b macro
/drivers/gpu/drm/radeon/
Dni_dma.c239 dma_cntl = RREG32(DMA_CNTL + reg_offset); in cayman_dma_resume()
241 WREG32(DMA_CNTL + reg_offset, dma_cntl); in cayman_dma_resume()
Dr600_dma.c160 dma_cntl = RREG32(DMA_CNTL); in r600_dma_resume()
162 WREG32(DMA_CNTL, dma_cntl); in r600_dma_resume()
Dsi.c5958 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5959 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
5960 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5961 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
6074 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set()
6075 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set()
6107 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl); in si_irq_set()
6108 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); in si_irq_set()
Dnid.h1323 #define DMA_CNTL 0xd02c macro
Dr600.c3626 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_disable_interrupt_state()
3627 WREG32(DMA_CNTL, tmp); in r600_disable_interrupt_state()
3808 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_irq_set()
3877 WREG32(DMA_CNTL, dma_cntl); in r600_irq_set()
Devergreen.c4472 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state()
4473 WREG32(DMA_CNTL, tmp); in evergreen_disable_interrupt_state()
4519 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_irq_set()
4568 WREG32(DMA_CNTL, dma_cntl); in evergreen_irq_set()
Dsid.h1833 #define DMA_CNTL 0xd02c macro
Devergreend.h1404 #define DMA_CNTL 0xd02c macro
Dr600d.h631 #define DMA_CNTL 0xd02c macro