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Searched refs:DP (Results 1 – 25 of 44) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dce/
Ddce_link_encoder.h53 SRI(DP_CONFIG, DP, id), \
54 SRI(DP_DPHY_CNTL, DP, id), \
55 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
56 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
57 SRI(DP_DPHY_SYM0, DP, id), \
58 SRI(DP_DPHY_SYM1, DP, id), \
59 SRI(DP_DPHY_SYM2, DP, id), \
60 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
61 SRI(DP_LINK_CNTL, DP, id), \
62 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
[all …]
Ddce_stream_encoder.h84 SRI(DP_MSE_RATE_CNTL, DP, id), \
85 SRI(DP_MSE_RATE_UPDATE, DP, id), \
86 SRI(DP_PIXEL_FORMAT, DP, id), \
87 SRI(DP_SEC_CNTL, DP, id), \
88 SRI(DP_STEER_FIFO, DP, id), \
89 SRI(DP_VID_M, DP, id), \
90 SRI(DP_VID_N, DP, id), \
91 SRI(DP_VID_STREAM_CNTL, DP, id), \
92 SRI(DP_VID_TIMING, DP, id), \
93 SRI(DP_SEC_AUD_N, DP, id), \
[all …]
/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_ethtool.c249 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" in bnx2x_get_vf_link_ksettings()
356 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" in bnx2x_get_link_ksettings()
385 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" in bnx2x_set_link_ksettings()
409 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_link_ksettings()
418 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_link_ksettings()
439 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_link_ksettings()
458 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_link_ksettings()
473 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); in bnx2x_set_link_ksettings()
483 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); in bnx2x_set_link_ksettings()
492 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); in bnx2x_set_link_ksettings()
[all …]
Dbnx2x_dcb.c131 DP(NETIF_MSG_LINK, "local_mib.error %x\n", error); in bnx2x_dump_dcbx_drv_param()
134 DP(NETIF_MSG_LINK, in bnx2x_dump_dcbx_drv_param()
137 DP(NETIF_MSG_LINK, in bnx2x_dump_dcbx_drv_param()
141 DP(NETIF_MSG_LINK, in bnx2x_dump_dcbx_drv_param()
146 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.pri_en_bitmap %x\n", in bnx2x_dump_dcbx_drv_param()
148 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.pfc_caps %x\n", in bnx2x_dump_dcbx_drv_param()
150 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.enabled %x\n", in bnx2x_dump_dcbx_drv_param()
153 DP(BNX2X_MSG_DCB, "dcbx_features.app.default_pri %x\n", in bnx2x_dump_dcbx_drv_param()
155 DP(BNX2X_MSG_DCB, "dcbx_features.app.tc_supported %x\n", in bnx2x_dump_dcbx_drv_param()
157 DP(BNX2X_MSG_DCB, "dcbx_features.app.enabled %x\n", in bnx2x_dump_dcbx_drv_param()
[all …]
Dbnx2x_link.c261 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n"); in bnx2x_check_lfa()
302 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n", in bnx2x_check_lfa()
311 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n", in bnx2x_check_lfa()
320 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n", in bnx2x_check_lfa()
331 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n", in bnx2x_check_lfa()
344 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n", in bnx2x_check_lfa()
357 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode, in bnx2x_check_lfa()
374 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); in bnx2x_get_epio()
391 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); in bnx2x_set_epio()
394 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); in bnx2x_set_epio()
[all …]
Dbnx2x_sriov.c100 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", in bnx2x_vf_igu_ack_sb()
105 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", in bnx2x_vf_igu_ack_sb()
119 DP(BNX2X_MSG_IOV, "Slowpath objects not yet initialized!\n"); in bnx2x_validate_vf_sp_objs()
131 DP(BNX2X_MSG_IOV, in bnx2x_vfop_qctor_dump_tx()
149 …DP(BNX2X_MSG_IOV, "VF[%d] Q_SETUP: rxq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, mtu=%d, buf-size=%d… in bnx2x_vfop_qctor_dump_rx()
241 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); in bnx2x_vf_queue_create()
250 DP(BNX2X_MSG_IOV, "queue was already up. Aborting gracefully\n"); in bnx2x_vf_queue_create()
283 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); in bnx2x_vf_queue_destroy()
292 DP(BNX2X_MSG_IOV, "queue was already stopped. Aborting gracefully\n"); in bnx2x_vf_queue_destroy()
344 DP(BNX2X_MSG_SP, "Failed to take vlan mac read head; continuing anyway\n"); in bnx2x_vf_vlan_credit()
[all …]
Dbnx2x_main.c398 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
406 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
416 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
424 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
434 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
441 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
451 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n", in bnx2x_dp_dmae()
868 DP(NETIF_MSG_IFDOWN, in bnx2x_hc_int_disable()
885 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); in bnx2x_igu_int_disable()
915 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); in bnx2x_panic_dump()
[all …]
Dbnx2x_sp.c75 DP(BNX2X_MSG_SP, "Setup the execution queue with the chunk length of %d\n", in bnx2x_exe_queue_init()
82 DP(BNX2X_MSG_SP, "Deleting an exe_queue element\n"); in bnx2x_exe_queue_free_elem()
129 DP(BNX2X_MSG_SP, "Preamble failed: %d\n", rc); in bnx2x_exe_queue_add()
190 DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list\n"); in bnx2x_exe_queue_step()
251 DP(BNX2X_MSG_SP, "Allocating a new exe_queue element\n"); in bnx2x_exe_queue_alloc_elem()
292 DP(BNX2X_MSG_SP, "waiting for state to become %d\n", state); in bnx2x_state_wait()
298 DP(BNX2X_MSG_SP, "exit (cnt %d)\n", 5000 - cnt); in bnx2x_state_wait()
434 DP(BNX2X_MSG_SP, "vlan_mac_lock writer - There are readers; Busy\n"); in __bnx2x_vlan_mac_h_write_trylock()
438 DP(BNX2X_MSG_SP, "vlan_mac_lock writer - Taken\n"); in __bnx2x_vlan_mac_h_write_trylock()
457 DP(BNX2X_MSG_SP, "vlan_mac_lock execute pending command with ramrod flags %lu\n", in __bnx2x_vlan_mac_h_exec_pending()
[all …]
Dbnx2x_vfpf.c45 DP(BNX2X_MSG_IOV, "preparing to send %d tlv over vf pf channel\n", in bnx2x_vfpf_prep()
62 DP(BNX2X_MSG_IOV, "done sending [%d] tlv over vf pf channel\n", in bnx2x_vfpf_finalize()
87 DP(BNX2X_MSG_IOV, "TLV list does not contain %d TLV\n", req_tlv); in bnx2x_search_tlv_list()
100 DP(BNX2X_MSG_IOV, "TLV number %d: type %d, length %d\n", i, in bnx2x_dp_tlv_list()
119 DP(BNX2X_MSG_IOV, "TLV number %d: type %d, length %d\n", i, in bnx2x_dp_tlv_list()
158 DP(BNX2X_MSG_IOV, "detecting channel down. Aborting message\n"); in bnx2x_send_msg2pf()
190 DP(BNX2X_MSG_SP, "Got a response from PF\n"); in bnx2x_send_msg2pf()
216 DP(BNX2X_MSG_IOV, "valid ME register value: 0x%08x\n", me_reg); in bnx2x_get_vf_id()
274 DP(BNX2X_MSG_SP, "attempting to acquire resources\n"); in bnx2x_vfpf_acquire()
294 DP(BNX2X_MSG_SP, "resources acquired\n"); in bnx2x_vfpf_acquire()
[all …]
Dbnx2x_cmn.c209 DP(NETIF_MSG_TX_DONE, "fp[%d]: pkt_idx %d buff @(%p)->skb %p\n", in bnx2x_free_tx_pkt()
296 DP(NETIF_MSG_TX_DONE, in bnx2x_tx_int()
371 DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n", in bnx2x_update_sge_prod()
402 DP(NETIF_MSG_RX_STATUS, in bnx2x_update_sge_prod()
489 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n", in bnx2x_tpa_start()
807 DP(NETIF_MSG_RX_STATUS, in bnx2x_tpa_stop()
821 DP(NETIF_MSG_RX_STATUS, in bnx2x_tpa_stop()
906 DP(NETIF_MSG_RX_STATUS, in bnx2x_rx_int()
942 DP(NETIF_MSG_RX_STATUS, in bnx2x_rx_int()
973 DP(NETIF_MSG_RX_STATUS, in bnx2x_rx_int()
[all …]
Dbnx2x_cmn.h57 DP(NETIF_MSG_HW, \
67 DP(NETIF_MSG_HW, \
531 DP(NETIF_MSG_RX_STATUS, in bnx2x_update_rx_prod()
650 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", in bnx2x_igu_ack_sb_gen()
713 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", in bnx2x_igu_ack_int()
942 DP(NETIF_MSG_IFUP, "Configuring ethertype 0x88a8 for BD\n"); in bnx2x_func_start()
952 DP(NETIF_MSG_IFUP, in bnx2x_func_start()
1174 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", in bnx2x_init_txdata()
1292 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, in bnx2x_extract_max_cfg()
1363 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); in bnx2x_update_drv_flags()
Dbnx2x_stats.c88 DP(BNX2X_MSG_STATS, "dumping stats:\n" in bnx2x_dp_stats()
104 DP(BNX2X_MSG_STATS, in bnx2x_dp_stats()
136 DP(BNX2X_MSG_STATS, "Sending statistics ramrod %d\n", in bnx2x_storm_stats_post()
828 DP(BNX2X_MSG_STATS, in bnx2x_hw_stats_update()
887 DP(BNX2X_MSG_STATS, in bnx2x_storm_stats_validate_counters()
894 DP(BNX2X_MSG_STATS, in bnx2x_storm_stats_validate_counters()
901 DP(BNX2X_MSG_STATS, in bnx2x_storm_stats_validate_counters()
908 DP(BNX2X_MSG_STATS, in bnx2x_storm_stats_validate_counters()
958 DP(BNX2X_MSG_STATS, "queue[%d]: ucast_sent 0x%x, bcast_sent 0x%x mcast_sent 0x%x\n", in bnx2x_storm_stats_update()
962 DP(BNX2X_MSG_STATS, "---------------\n"); in bnx2x_storm_stats_update()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_link_encoder.h46 SRI(DP_CONFIG, DP, id), \
47 SRI(DP_DPHY_CNTL, DP, id), \
48 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
49 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
50 SRI(DP_DPHY_SYM0, DP, id), \
51 SRI(DP_DPHY_SYM1, DP, id), \
52 SRI(DP_DPHY_SYM2, DP, id), \
53 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
54 SRI(DP_LINK_CNTL, DP, id), \
55 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
[all …]
Ddcn10_stream_encoder.h73 SRI(DP_DB_CNTL, DP, id), \
74 SRI(DP_MSA_MISC, DP, id), \
75 SRI(DP_MSA_COLORIMETRY, DP, id), \
76 SRI(DP_MSA_TIMING_PARAM1, DP, id), \
77 SRI(DP_MSA_TIMING_PARAM2, DP, id), \
78 SRI(DP_MSA_TIMING_PARAM3, DP, id), \
79 SRI(DP_MSA_TIMING_PARAM4, DP, id), \
80 SRI(DP_MSE_RATE_CNTL, DP, id), \
81 SRI(DP_MSE_RATE_UPDATE, DP, id), \
82 SRI(DP_PIXEL_FORMAT, DP, id), \
[all …]
/drivers/gpu/drm/gma500/
Dcdv_intel_dp.c259 uint32_t DP; member
1048 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; in cdv_intel_dp_mode_set()
1049 intel_dp->DP |= intel_dp->color_range; in cdv_intel_dp_mode_set()
1052 intel_dp->DP |= DP_SYNC_HS_HIGH; in cdv_intel_dp_mode_set()
1054 intel_dp->DP |= DP_SYNC_VS_HIGH; in cdv_intel_dp_mode_set()
1056 intel_dp->DP |= DP_LINK_TRAIN_OFF; in cdv_intel_dp_mode_set()
1060 intel_dp->DP |= DP_PORT_WIDTH_1; in cdv_intel_dp_mode_set()
1063 intel_dp->DP |= DP_PORT_WIDTH_2; in cdv_intel_dp_mode_set()
1066 intel_dp->DP |= DP_PORT_WIDTH_4; in cdv_intel_dp_mode_set()
1070 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; in cdv_intel_dp_mode_set()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_stream_encoder.h37 SRI(DP_DSC_CNTL, DP, id), \
38 SRI(DP_DSC_BYTES_PER_PIXEL, DP, id), \
40 SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
42 SRI(DP_SEC_FRAMING4, DP, id)
/drivers/gpu/drm/rockchip/
DKconfig24 bool "Rockchip specific extensions for Analogix DP driver"
27 for the Analogix Core DP driver. If you want to enable DP
31 bool "Rockchip cdn DP"
35 for the cdn DP driver. If you want to enable Dp on
/drivers/gpu/drm/i915/display/
Dintel_dp.c732 u32 DP; in vlv_power_sequencer_kick() local
745 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; in vlv_power_sequencer_kick()
746 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; in vlv_power_sequencer_kick()
747 DP |= DP_PORT_WIDTH(1); in vlv_power_sequencer_kick()
748 DP |= DP_LINK_TRAIN_PAT_1; in vlv_power_sequencer_kick()
751 DP |= DP_PIPE_SEL_CHV(pipe); in vlv_power_sequencer_kick()
753 DP |= DP_PIPE_SEL(pipe); in vlv_power_sequencer_kick()
779 I915_WRITE(intel_dp->output_reg, DP); in vlv_power_sequencer_kick()
782 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); in vlv_power_sequencer_kick()
785 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); in vlv_power_sequencer_kick()
[all …]
/drivers/block/
Dfloppy.c309 #define DP (&drive_params[current_drive]) macro
633 if (DP->flags & DEBUGT) in debugt()
829 if (DP->select_delay) in twaddle()
952 if (DP->select_delay) in scandrives()
1011 debug_dcl(DP->flags, "calling disk change from watchdog\n"); in fd_watchdog()
1312 srt = 16 - DIV_ROUND_UP(DP->srt * scale_dtr / 1000, NOMINAL_DTR); in fdc_specify()
1319 hlt = DIV_ROUND_UP(DP->hlt * scale_dtr / 2, NOMINAL_DTR); in fdc_specify()
1325 hut = DIV_ROUND_UP(DP->hut * scale_dtr / 16, NOMINAL_DTR); in fdc_specify()
1432 if (DP->flags & FTD_MSG) in interpret_errors()
1435 } else if (*errors >= DP->max_errors.reporting) { in interpret_errors()
[all …]
/drivers/net/wan/
Dsbni.h10 #define DP( A ) A macro
12 #define DP( A ) macro
/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dsorgv100.c70 case 8: state->proto = DP; state->link = 1; break; in gv100_sor_state()
71 case 9: state->proto = DP; state->link = 2; break; in gv100_sor_state()
Dsorgf119.c148 case 8: state->proto = DP; state->link = 1; break; in gf119_sor_state()
149 case 9: state->proto = DP; state->link = 2; break; in gf119_sor_state()
Dsorg94.c249 case 8: state->proto = DP; state->link = 1; break; in g94_sor_state()
250 case 9: state->proto = DP; state->link = 2; break; in g94_sor_state()
/drivers/gpu/drm/exynos/
DKconfig65 bool "EXYNOS specific extensions for Analogix DP driver"
71 This enables support for DP device.
/drivers/gpu/drm/amd/display/
DTODO82 15. Move DP/HDMI dual mode adaptors to drm_dp_dual_mode_helper.c. See
93 18. There's a pile of sink handling code, both for DP and HDMI where I didn't
97 issue with DC - other drivers, especially around DP sink handling, are equally

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