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Searched refs:DPIO_CH1 (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_dpio_phy.c168 [DPIO_CH1] = { .port = PORT_C },
255 port == phy_info->channel[DPIO_CH1].port) { in bxt_port_to_phy_channel()
257 *ch = DPIO_CH1; in bxt_port_to_phy_channel()
799 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); in chv_phy_pre_pll_enable()
814 if (ch == DPIO_CH1) in chv_phy_pre_pll_enable()
822 if (ch == DPIO_CH1) in chv_phy_pre_pll_enable()
947 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); in chv_phy_release_cl2_override()
Dintel_display_power.c1309 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | in assert_chv_phy_status()
1310 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | in assert_chv_phy_status()
1311 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); in assert_chv_phy_status()
1325 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) in assert_chv_phy_status()
1326 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); in assert_chv_phy_status()
1331 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) in assert_chv_phy_status()
1340 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && in assert_chv_phy_status()
1342 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); in assert_chv_phy_status()
1352 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) in assert_chv_phy_status()
1353 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); in assert_chv_phy_status()
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Dintel_display_types.h1305 return DPIO_CH1; in vlv_dport_to_channel()
1333 return DPIO_CH1; in vlv_pipe_to_channel()
Dintel_display.h236 DPIO_CH1 enumerator
/drivers/gpu/drm/i915/gvt/
Dhandlers.c3206 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT); in init_bxt_mmio_info()
3207 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT); in init_bxt_mmio_info()
3208 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT); in init_bxt_mmio_info()
3209 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); in init_bxt_mmio_info()
3210 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT); in init_bxt_mmio_info()
3211 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT); in init_bxt_mmio_info()
3212 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, in init_bxt_mmio_info()
3214 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT); in init_bxt_mmio_info()
3215 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); in init_bxt_mmio_info()
3216 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT, in init_bxt_mmio_info()
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