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Searched refs:DP_SEC_CNTL (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.c739 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); in enc1_stream_encoder_update_dp_info_packets()
740 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); in enc1_stream_encoder_update_dp_info_packets()
741 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); in enc1_stream_encoder_update_dp_info_packets()
751 value = REG_READ(DP_SEC_CNTL); in enc1_stream_encoder_update_dp_info_packets()
753 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); in enc1_stream_encoder_update_dp_info_packets()
845 value = REG_READ(DP_SEC_CNTL); in enc1_stream_encoder_send_immediate_sdp_message()
847 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); in enc1_stream_encoder_send_immediate_sdp_message()
857 REG_SET_10(DP_SEC_CNTL, 0, in enc1_stream_encoder_stop_dp_info_packets()
872 value = REG_READ(DP_SEC_CNTL); in enc1_stream_encoder_stop_dp_info_packets()
874 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); in enc1_stream_encoder_stop_dp_info_packets()
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Ddcn10_link_encoder.h60 SRI(DP_SEC_CNTL, DP, id), \
102 uint32_t DP_SEC_CNTL; member
Ddcn10_stream_encoder.h83 SRI(DP_SEC_CNTL, DP, id), \
128 uint32_t DP_SEC_CNTL; member
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.c877 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); in dce110_stream_encoder_update_dp_info_packets()
878 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); in dce110_stream_encoder_update_dp_info_packets()
879 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); in dce110_stream_encoder_update_dp_info_packets()
888 value = REG_READ(DP_SEC_CNTL); in dce110_stream_encoder_update_dp_info_packets()
890 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); in dce110_stream_encoder_update_dp_info_packets()
901 REG_SET_7(DP_SEC_CNTL, 0, in dce110_stream_encoder_stop_dp_info_packets()
914 value = REG_READ(DP_SEC_CNTL); in dce110_stream_encoder_stop_dp_info_packets()
916 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); in dce110_stream_encoder_stop_dp_info_packets()
1504 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); in dce110_se_enable_dp_audio()
1507 REG_UPDATE_2(DP_SEC_CNTL, in dce110_se_enable_dp_audio()
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Ddce_stream_encoder.h87 SRI(DP_SEC_CNTL, DP, id), \
154 SE_SF(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
155 SE_SF(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
156 SE_SF(DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
157 SE_SF(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
158 SE_SF(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
159 SE_SF(DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\
160 SE_SF(DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
198 SE_SF(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
199 SE_SF(DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
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Ddce_link_encoder.h67 SRI(DP_SEC_CNTL, DP, id), \
148 uint32_t DP_SEC_CNTL; member
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_stream_encoder.c332 REG_UPDATE_2(DP_SEC_CNTL, in enc2_dp_set_dsc_pps_info_packet()
337 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, 0); in enc2_dp_set_dsc_pps_info_packet()
359 REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp_pps_enable); in enc2_read_state()
360 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); in enc2_read_state()
436 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); in enc2_stream_encoder_update_dp_info_packets()
/drivers/gpu/drm/amd/amdgpu/
Ddce_v6_0.c1617 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); in dce_v6_0_audio_dp_enable()
1618 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1); in dce_v6_0_audio_dp_enable()
1619 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1); in dce_v6_0_audio_dp_enable()
1620 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); in dce_v6_0_audio_dp_enable()