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Searched refs:DP_TP_CTL (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_ddi.c1110 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
1173 temp = I915_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
1176 I915_WRITE(DP_TP_CTL(PORT_E), temp); in hsw_fdi_link_train()
1177 POSTING_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
1190 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
3138 val = I915_READ(DP_TP_CTL(port)); in intel_ddi_enable_fec()
3140 I915_WRITE(DP_TP_CTL(port), val); in intel_ddi_enable_fec()
3157 val = I915_READ(DP_TP_CTL(port)); in intel_ddi_disable_fec_state()
3159 I915_WRITE(DP_TP_CTL(port), val); in intel_ddi_disable_fec_state()
3160 POSTING_READ(DP_TP_CTL(port)); in intel_ddi_disable_fec_state()
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Dintel_dp.c3318 u32 temp = I915_READ(DP_TP_CTL(port)); in _intel_dp_set_link_train()
3344 I915_WRITE(DP_TP_CTL(port), temp); in _intel_dp_set_link_train()
4042 val = I915_READ(DP_TP_CTL(port)); in intel_dp_set_idle_link_train()
4045 I915_WRITE(DP_TP_CTL(port), val); in intel_dp_set_idle_link_train()
/drivers/gpu/drm/i915/gvt/
Dhandlers.c566 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); in fdi_auto_training_started()
685 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
2453 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2454 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2455 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2456 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2457 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
/drivers/gpu/drm/i915/
Di915_reg.h9438 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) macro