1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Driver for the Synopsys DesignWare AHB DMA Controller
4 *
5 * Copyright (C) 2005-2007 Atmel Corporation
6 * Copyright (C) 2010-2011 ST Microelectronics
7 * Copyright (C) 2016 Intel Corporation
8 */
9
10 #include <linux/bitops.h>
11 #include <linux/interrupt.h>
12 #include <linux/dmaengine.h>
13
14 #include <linux/io-64-nonatomic-hi-lo.h>
15
16 #include "internal.h"
17
18 #define DW_DMA_MAX_NR_REQUESTS 16
19
20 /* flow controller */
21 enum dw_dma_fc {
22 DW_DMA_FC_D_M2M,
23 DW_DMA_FC_D_M2P,
24 DW_DMA_FC_D_P2M,
25 DW_DMA_FC_D_P2P,
26 DW_DMA_FC_P_P2M,
27 DW_DMA_FC_SP_P2P,
28 DW_DMA_FC_P_M2P,
29 DW_DMA_FC_DP_P2P,
30 };
31
32 /*
33 * Redefine this macro to handle differences between 32- and 64-bit
34 * addressing, big vs. little endian, etc.
35 */
36 #define DW_REG(name) u32 name; u32 __pad_##name
37
38 /* Hardware register definitions. */
39 struct dw_dma_chan_regs {
40 DW_REG(SAR); /* Source Address Register */
41 DW_REG(DAR); /* Destination Address Register */
42 DW_REG(LLP); /* Linked List Pointer */
43 u32 CTL_LO; /* Control Register Low */
44 u32 CTL_HI; /* Control Register High */
45 DW_REG(SSTAT);
46 DW_REG(DSTAT);
47 DW_REG(SSTATAR);
48 DW_REG(DSTATAR);
49 u32 CFG_LO; /* Configuration Register Low */
50 u32 CFG_HI; /* Configuration Register High */
51 DW_REG(SGR);
52 DW_REG(DSR);
53 };
54
55 struct dw_dma_irq_regs {
56 DW_REG(XFER);
57 DW_REG(BLOCK);
58 DW_REG(SRC_TRAN);
59 DW_REG(DST_TRAN);
60 DW_REG(ERROR);
61 };
62
63 struct dw_dma_regs {
64 /* per-channel registers */
65 struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
66
67 /* irq handling */
68 struct dw_dma_irq_regs RAW; /* r */
69 struct dw_dma_irq_regs STATUS; /* r (raw & mask) */
70 struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */
71 struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */
72
73 DW_REG(STATUS_INT); /* r */
74
75 /* software handshaking */
76 DW_REG(REQ_SRC);
77 DW_REG(REQ_DST);
78 DW_REG(SGL_REQ_SRC);
79 DW_REG(SGL_REQ_DST);
80 DW_REG(LAST_SRC);
81 DW_REG(LAST_DST);
82
83 /* miscellaneous */
84 DW_REG(CFG);
85 DW_REG(CH_EN);
86 DW_REG(ID);
87 DW_REG(TEST);
88
89 /* iDMA 32-bit support */
90 DW_REG(CLASS_PRIORITY0);
91 DW_REG(CLASS_PRIORITY1);
92
93 /* optional encoded params, 0x3c8..0x3f7 */
94 u32 __reserved;
95
96 /* per-channel configuration registers */
97 u32 DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
98 u32 MULTI_BLK_TYPE;
99 u32 MAX_BLK_SIZE;
100
101 /* top-level parameters */
102 u32 DW_PARAMS;
103
104 /* component ID */
105 u32 COMP_TYPE;
106 u32 COMP_VERSION;
107
108 /* iDMA 32-bit support */
109 DW_REG(FIFO_PARTITION0);
110 DW_REG(FIFO_PARTITION1);
111
112 DW_REG(SAI_ERR);
113 DW_REG(GLOBAL_CFG);
114 };
115
116 /* Bitfields in DW_PARAMS */
117 #define DW_PARAMS_NR_CHAN 8 /* number of channels */
118 #define DW_PARAMS_NR_MASTER 11 /* number of AHB masters */
119 #define DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n))
120 #define DW_PARAMS_DATA_WIDTH1 15 /* master 1 data width */
121 #define DW_PARAMS_DATA_WIDTH2 17 /* master 2 data width */
122 #define DW_PARAMS_DATA_WIDTH3 19 /* master 3 data width */
123 #define DW_PARAMS_DATA_WIDTH4 21 /* master 4 data width */
124 #define DW_PARAMS_EN 28 /* encoded parameters */
125
126 /* Bitfields in DWC_PARAMS */
127 #define DWC_PARAMS_MBLK_EN 11 /* multi block transfer */
128
129 /* bursts size */
130 enum dw_dma_msize {
131 DW_DMA_MSIZE_1,
132 DW_DMA_MSIZE_4,
133 DW_DMA_MSIZE_8,
134 DW_DMA_MSIZE_16,
135 DW_DMA_MSIZE_32,
136 DW_DMA_MSIZE_64,
137 DW_DMA_MSIZE_128,
138 DW_DMA_MSIZE_256,
139 };
140
141 /* Bitfields in LLP */
142 #define DWC_LLP_LMS(x) ((x) & 3) /* list master select */
143 #define DWC_LLP_LOC(x) ((x) & ~3) /* next lli */
144
145 /* Bitfields in CTL_LO */
146 #define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */
147 #define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */
148 #define DWC_CTLL_SRC_WIDTH(n) ((n)<<4)
149 #define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */
150 #define DWC_CTLL_DST_DEC (1<<7)
151 #define DWC_CTLL_DST_FIX (2<<7)
152 #define DWC_CTLL_SRC_INC (0<<9) /* SAR update/not */
153 #define DWC_CTLL_SRC_DEC (1<<9)
154 #define DWC_CTLL_SRC_FIX (2<<9)
155 #define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */
156 #define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
157 #define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */
158 #define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */
159 #define DWC_CTLL_FC(n) ((n) << 20)
160 #define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */
161 #define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
162 #define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
163 #define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */
164 /* plus 4 transfer types for peripheral-as-flow-controller */
165 #define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */
166 #define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */
167 #define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */
168 #define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */
169
170 /* Bitfields in CTL_HI */
171 #define DWC_CTLH_BLOCK_TS_MASK GENMASK(11, 0)
172 #define DWC_CTLH_BLOCK_TS(x) ((x) & DWC_CTLH_BLOCK_TS_MASK)
173 #define DWC_CTLH_DONE (1 << 12)
174
175 /* Bitfields in CFG_LO */
176 #define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */
177 #define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */
178 #define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */
179 #define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */
180 #define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */
181 #define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */
182 #define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
183 #define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
184 #define DWC_CFGL_LOCK_CH_XACT (2 << 12)
185 #define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
186 #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
187 #define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
188 #define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
189 #define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
190 #define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
191 #define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
192 #define DWC_CFGL_MAX_BURST(x) ((x) << 20)
193 #define DWC_CFGL_RELOAD_SAR (1 << 30)
194 #define DWC_CFGL_RELOAD_DAR (1 << 31)
195
196 /* Bitfields in CFG_HI */
197 #define DWC_CFGH_FCMODE (1 << 0)
198 #define DWC_CFGH_FIFO_MODE (1 << 1)
199 #define DWC_CFGH_PROTCTL(x) ((x) << 2)
200 #define DWC_CFGH_PROTCTL_DATA (0 << 2) /* data access - always set */
201 #define DWC_CFGH_PROTCTL_PRIV (1 << 2) /* privileged -> AHB HPROT[1] */
202 #define DWC_CFGH_PROTCTL_BUFFER (2 << 2) /* bufferable -> AHB HPROT[2] */
203 #define DWC_CFGH_PROTCTL_CACHE (4 << 2) /* cacheable -> AHB HPROT[3] */
204 #define DWC_CFGH_DS_UPD_EN (1 << 5)
205 #define DWC_CFGH_SS_UPD_EN (1 << 6)
206 #define DWC_CFGH_SRC_PER(x) ((x) << 7)
207 #define DWC_CFGH_DST_PER(x) ((x) << 11)
208
209 /* Bitfields in SGR */
210 #define DWC_SGR_SGI(x) ((x) << 0)
211 #define DWC_SGR_SGC(x) ((x) << 20)
212
213 /* Bitfields in DSR */
214 #define DWC_DSR_DSI(x) ((x) << 0)
215 #define DWC_DSR_DSC(x) ((x) << 20)
216
217 /* Bitfields in CFG */
218 #define DW_CFG_DMA_EN (1 << 0)
219
220 /* iDMA 32-bit support */
221
222 /* bursts size */
223 enum idma32_msize {
224 IDMA32_MSIZE_1,
225 IDMA32_MSIZE_2,
226 IDMA32_MSIZE_4,
227 IDMA32_MSIZE_8,
228 IDMA32_MSIZE_16,
229 IDMA32_MSIZE_32,
230 };
231
232 /* Bitfields in CTL_HI */
233 #define IDMA32C_CTLH_BLOCK_TS_MASK GENMASK(16, 0)
234 #define IDMA32C_CTLH_BLOCK_TS(x) ((x) & IDMA32C_CTLH_BLOCK_TS_MASK)
235 #define IDMA32C_CTLH_DONE (1 << 17)
236
237 /* Bitfields in CFG_LO */
238 #define IDMA32C_CFGL_DST_BURST_ALIGN (1 << 0) /* dst burst align */
239 #define IDMA32C_CFGL_SRC_BURST_ALIGN (1 << 1) /* src burst align */
240 #define IDMA32C_CFGL_CH_DRAIN (1 << 10) /* drain FIFO */
241 #define IDMA32C_CFGL_DST_OPT_BL (1 << 20) /* optimize dst burst length */
242 #define IDMA32C_CFGL_SRC_OPT_BL (1 << 21) /* optimize src burst length */
243
244 /* Bitfields in CFG_HI */
245 #define IDMA32C_CFGH_SRC_PER(x) ((x) << 0)
246 #define IDMA32C_CFGH_DST_PER(x) ((x) << 4)
247 #define IDMA32C_CFGH_RD_ISSUE_THD(x) ((x) << 8)
248 #define IDMA32C_CFGH_RW_ISSUE_THD(x) ((x) << 18)
249 #define IDMA32C_CFGH_SRC_PER_EXT(x) ((x) << 28) /* src peripheral extension */
250 #define IDMA32C_CFGH_DST_PER_EXT(x) ((x) << 30) /* dst peripheral extension */
251
252 /* Bitfields in FIFO_PARTITION */
253 #define IDMA32C_FP_PSIZE_CH0(x) ((x) << 0)
254 #define IDMA32C_FP_PSIZE_CH1(x) ((x) << 13)
255 #define IDMA32C_FP_UPDATE (1 << 26)
256
257 enum dw_dmac_flags {
258 DW_DMA_IS_CYCLIC = 0,
259 DW_DMA_IS_SOFT_LLP = 1,
260 DW_DMA_IS_PAUSED = 2,
261 DW_DMA_IS_INITIALIZED = 3,
262 };
263
264 struct dw_dma_chan {
265 struct dma_chan chan;
266 void __iomem *ch_regs;
267 u8 mask;
268 u8 priority;
269 enum dma_transfer_direction direction;
270
271 /* software emulation of the LLP transfers */
272 struct list_head *tx_node_active;
273
274 spinlock_t lock;
275
276 /* these other elements are all protected by lock */
277 unsigned long flags;
278 struct list_head active_list;
279 struct list_head queue;
280
281 unsigned int descs_allocated;
282
283 /* hardware configuration */
284 unsigned int block_size;
285 bool nollp;
286
287 /* custom slave configuration */
288 struct dw_dma_slave dws;
289
290 /* configuration passed via .device_config */
291 struct dma_slave_config dma_sconfig;
292 };
293
294 static inline struct dw_dma_chan_regs __iomem *
__dwc_regs(struct dw_dma_chan * dwc)295 __dwc_regs(struct dw_dma_chan *dwc)
296 {
297 return dwc->ch_regs;
298 }
299
300 #define channel_readl(dwc, name) \
301 readl(&(__dwc_regs(dwc)->name))
302 #define channel_writel(dwc, name, val) \
303 writel((val), &(__dwc_regs(dwc)->name))
304
to_dw_dma_chan(struct dma_chan * chan)305 static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
306 {
307 return container_of(chan, struct dw_dma_chan, chan);
308 }
309
310 struct dw_dma {
311 struct dma_device dma;
312 char name[20];
313 void __iomem *regs;
314 struct dma_pool *desc_pool;
315 struct tasklet_struct tasklet;
316
317 /* channels */
318 struct dw_dma_chan *chan;
319 u8 all_chan_mask;
320 u8 in_use;
321
322 /* Channel operations */
323 void (*initialize_chan)(struct dw_dma_chan *dwc);
324 void (*suspend_chan)(struct dw_dma_chan *dwc, bool drain);
325 void (*resume_chan)(struct dw_dma_chan *dwc, bool drain);
326 u32 (*prepare_ctllo)(struct dw_dma_chan *dwc);
327 void (*encode_maxburst)(struct dw_dma_chan *dwc, u32 *maxburst);
328 u32 (*bytes2block)(struct dw_dma_chan *dwc, size_t bytes,
329 unsigned int width, size_t *len);
330 size_t (*block2bytes)(struct dw_dma_chan *dwc, u32 block, u32 width);
331
332 /* Device operations */
333 void (*set_device_name)(struct dw_dma *dw, int id);
334 void (*disable)(struct dw_dma *dw);
335 void (*enable)(struct dw_dma *dw);
336
337 /* platform data */
338 struct dw_dma_platform_data *pdata;
339 };
340
__dw_regs(struct dw_dma * dw)341 static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
342 {
343 return dw->regs;
344 }
345
346 #define dma_readl(dw, name) \
347 readl(&(__dw_regs(dw)->name))
348 #define dma_writel(dw, name, val) \
349 writel((val), &(__dw_regs(dw)->name))
350
351 #define idma32_readq(dw, name) \
352 hi_lo_readq(&(__dw_regs(dw)->name))
353 #define idma32_writeq(dw, name, val) \
354 hi_lo_writeq((val), &(__dw_regs(dw)->name))
355
356 #define channel_set_bit(dw, reg, mask) \
357 dma_writel(dw, reg, ((mask) << 8) | (mask))
358 #define channel_clear_bit(dw, reg, mask) \
359 dma_writel(dw, reg, ((mask) << 8) | 0)
360
to_dw_dma(struct dma_device * ddev)361 static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
362 {
363 return container_of(ddev, struct dw_dma, dma);
364 }
365
366 /* LLI == Linked List Item; a.k.a. DMA block descriptor */
367 struct dw_lli {
368 /* values that are not changed by hardware */
369 __le32 sar;
370 __le32 dar;
371 __le32 llp; /* chain to next lli */
372 __le32 ctllo;
373 /* values that may get written back: */
374 __le32 ctlhi;
375 /* sstat and dstat can snapshot peripheral register state.
376 * silicon config may discard either or both...
377 */
378 __le32 sstat;
379 __le32 dstat;
380 };
381
382 struct dw_desc {
383 /* FIRST values the hardware uses */
384 struct dw_lli lli;
385
386 #define lli_set(d, reg, v) ((d)->lli.reg |= cpu_to_le32(v))
387 #define lli_clear(d, reg, v) ((d)->lli.reg &= ~cpu_to_le32(v))
388 #define lli_read(d, reg) le32_to_cpu((d)->lli.reg)
389 #define lli_write(d, reg, v) ((d)->lli.reg = cpu_to_le32(v))
390
391 /* THEN values for driver housekeeping */
392 struct list_head desc_node;
393 struct list_head tx_list;
394 struct dma_async_tx_descriptor txd;
395 size_t len;
396 size_t total_len;
397 u32 residue;
398 };
399
400 #define to_dw_desc(h) list_entry(h, struct dw_desc, desc_node)
401
402 static inline struct dw_desc *
txd_to_dw_desc(struct dma_async_tx_descriptor * txd)403 txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
404 {
405 return container_of(txd, struct dw_desc, txd);
406 }
407