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Searched refs:HDMI_ACR_CTS_48 (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.h185 SE_SF(HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
265 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
461 uint8_t HDMI_ACR_CTS_48; member
592 uint32_t HDMI_ACR_CTS_48; member
Ddce_stream_encoder.c1412 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); in dce110_se_setup_hdmi_audio()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.h237 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
427 type HDMI_ACR_CTS_48;\
Ddcn10_stream_encoder.c1347 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); in enc1_se_setup_hdmi_audio()
/drivers/gpu/drm/radeon/
Devergreen_hdmi.c93 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); in evergreen_hdmi_update_acr()
Drv770d.h796 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) macro
Devergreend.h650 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) macro
/drivers/gpu/drm/amd/amdgpu/
Ddce_v6_0.c1421 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); in dce_v6_0_audio_set_acr()
Ddce_v11_0.c1531 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); in dce_v11_0_afmt_update_ACR()
Ddce_v10_0.c1489 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); in dce_v10_0_afmt_update_ACR()