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Searched refs:HDMI_ACR_N_32 (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.h182 SE_SF(HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
262 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
458 uint8_t HDMI_ACR_N_32; member
589 uint32_t HDMI_ACR_N_32; member
Ddce_stream_encoder.c1403 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); in dce110_se_setup_hdmi_audio()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.h234 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
424 type HDMI_ACR_N_32;\
Ddcn10_stream_encoder.c1338 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); in enc1_se_setup_hdmi_audio()
/drivers/gpu/drm/radeon/
Drv770d.h790 # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) macro
Devergreend.h644 # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) macro
/drivers/gpu/drm/amd/amdgpu/
Ddce_v6_0.c1410 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); in dce_v6_0_audio_set_acr()
Ddce_v11_0.c1520 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); in dce_v11_0_afmt_update_ACR()
Ddce_v10_0.c1478 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); in dce_v10_0_afmt_update_ACR()