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Searched refs:INTR_MASK (Results 1 – 16 of 16) sorted by relevance

/drivers/net/ethernet/marvell/octeontx2/af/
Drvu.c1749 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs)); in rvu_enable_mbox_intr()
1753 INTR_MASK(hw->total_pfs) & ~1ULL); in rvu_enable_mbox_intr()
1972 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); in rvu_unregister_interrupts()
1976 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); in rvu_unregister_interrupts()
1980 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); in rvu_unregister_interrupts()
2065 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs)); in rvu_register_interrupts()
2068 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); in rvu_register_interrupts()
2085 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs)); in rvu_register_interrupts()
2088 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); in rvu_register_interrupts()
2231 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs)); in rvu_disable_afvf_intr()
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Dmbox.h37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) macro
/drivers/net/ethernet/chelsio/cxgb3/
Dvsc8211.c71 #define INTR_MASK (CFG_CHG_INTR_MASK | VSC_INTR_TX_FIFO | VSC_INTR_RX_FIFO | \ macro
100 INTR_MASK); in vsc8211_intr_enable()
331 cause &= INTR_MASK; in vsc8211_intr_handler()
/drivers/staging/qlge/
Dqlge_mpi.c227 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16)); in ql_idc_req_aen()
294 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16)); in ql_link_up()
540 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16)); in ql_mailbox_command()
606 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI); in ql_mailbox_command()
1244 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16)); in ql_mpi_work()
1258 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI); in ql_mpi_work()
Dqlge.h812 INTR_MASK = 0x38, enumerator
Dqlge_main.c2530 (ql_read32(qdev, INTR_MASK) & INTR_MASK_PI)) { in qlge_isr()
2538 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16)); in qlge_isr()
3774 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI); in ql_adapter_initialize()
Dqlge_dbg.c1479 DUMP_REG(qdev, INTR_MASK); in ql_dump_regs()
/drivers/usb/host/
Dehci-hcd.c92 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) macro
643 ehci_writel(ehci, INTR_MASK, in ehci_run()
717 masked_status = status & (INTR_MASK | STS_FLR); in ehci_irq()
1138 int mask = INTR_MASK; in ehci_resume()
Dehci-hub.c356 mask = INTR_MASK; in ehci_bus_suspend()
504 ehci_writel(ehci, INTR_MASK, &ehci->regs->intr_enable); in ehci_bus_resume()
Doxu210hp-hcd.c150 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) macro
2870 status &= INTR_MASK; in oxu210_hcd_irq()
3165 writel(INTR_MASK, &oxu->regs->intr_enable); /* Turn On Interrupts */ in oxu_run()
3915 mask = INTR_MASK; in oxu_bus_suspend()
4002 writel(INTR_MASK, &oxu->regs->intr_enable); in oxu_bus_resume()
Dfotg210-hcd.c77 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) macro
5076 fotg210_writel(fotg210, INTR_MASK, in fotg210_run()
5140 masked_status = status & (INTR_MASK | STS_FLR); in fotg210_irq()
/drivers/net/ethernet/cavium/thunder/
Dnic_main.c103 #define INTR_MASK(vfs) ((vfs < 64) ? (BIT_ULL(vfs) - 1) : (~0ull)) in nic_enable_mbx_intr() macro
106 nic_reg_write(nic, NIC_PF_MAILBOX_INT, INTR_MASK(vf_cnt)); in nic_enable_mbx_intr()
109 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, INTR_MASK(vf_cnt)); in nic_enable_mbx_intr()
113 INTR_MASK(vf_cnt - 64)); in nic_enable_mbx_intr()
115 INTR_MASK(vf_cnt - 64)); in nic_enable_mbx_intr()
/drivers/gpu/drm/rockchip/
Drockchip_drm_vop.h185 #define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \ macro
Drockchip_drm_vop.c1448 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); in vop_isr()
1701 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); in vop_initial()
1702 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); in vop_initial()
/drivers/input/keyboard/
Dspear-keyboard.c32 #define INTR_MASK 0x54 macro
/drivers/staging/android/
Dvsoc.c50 INTR_MASK = 0x00, /* Interrupt Mask */ enumerator