Searched refs:INTR_STATUS (Results 1 – 7 of 7) sorted by relevance
| /drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hwio.h | 15 #define INTR_STATUS 0x014 macro
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| D | dpu_hw_interrupts.c | 199 MDP_SSPP_TOP0_OFF+INTR_STATUS
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| /drivers/i3c/master/ |
| D | dw-i3c-master.c | 98 #define INTR_STATUS 0x3c macro
624 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_bus_init()
1069 status = readl(master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1072 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1079 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1133 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_probe()
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| /drivers/staging/media/tegra-vde/ |
| D | vde.c | 33 #define INTR_STATUS 0x18 macro
147 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev()
154 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev()
164 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev()
330 tegra_vde_writel(vde, 0x0003FC00, vde->bsev, INTR_STATUS); in tegra_vde_setup_hw_context()
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| /drivers/mtd/nand/raw/ |
| D | denali.h | 208 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) macro
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| D | denali.c | 112 iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); in denali_clear_irq()
133 irq_status = ioread32(denali->reg + INTR_STATUS(i)); in denali_isr()
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| /drivers/staging/android/ |
| D | vsoc.c | 51 INTR_STATUS = 0x04, /* Interrupt Status */ enumerator
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