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Searched refs:MC_SEQ_RD_CTL_D1 (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/radeon/
Dbtcd.h110 #define MC_SEQ_RD_CTL_D1 0x28b8 macro
Dbtc_dpm.c1876 case MC_SEQ_RD_CTL_D1 >> 2: in btc_check_s0_mc_reg_index()
2036 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); in btc_initialize_mc_reg_table()
Dnid.h786 #define MC_SEQ_RD_CTL_D1 0x28b8 macro
Dsid.h547 #define MC_SEQ_RD_CTL_D1 0x28b8 macro
Dcikd.h660 #define MC_SEQ_RD_CTL_D1 0x28b8 macro
Devergreend.h292 #define MC_SEQ_RD_CTL_D1 0x28b8 macro
Dni_dpm.c2788 case MC_SEQ_RD_CTL_D1 >> 2: in ni_check_s0_mc_reg_index()
2893 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); in ni_initialize_mc_reg_table()
Dcypress_dpm.c993 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D1 >> 2; in cypress_set_mc_reg_address_table()
Dsi_dpm.c5446 case MC_SEQ_RD_CTL_D1 >> 2: in si_check_s0_mc_reg_index()
5555 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); in si_initialize_mc_reg_table()
Dci_dpm.c4445 case MC_SEQ_RD_CTL_D1 >> 2: in ci_check_s0_mc_reg_index()
4652 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); in ci_initialize_mc_reg_table()
/drivers/gpu/drm/amd/amdgpu/
Dsid.h549 #define MC_SEQ_RD_CTL_D1 0xA2E macro
Dsi_dpm.c5900 case MC_SEQ_RD_CTL_D1: in si_check_s0_mc_reg_index()
6009 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); in si_initialize_mc_reg_table()