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Searched refs:PFD0_CLKGATE (Results 1 – 1 of 1) sorted by relevance

/drivers/clk/imx/
Dclk-imx6q.c392 #define PFD0_CLKGATE BIT(7) macro
406 reg |= PFD0_CLKGATE | PFD1_CLKGATE; in disable_anatop_clocks()
408 reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE; in disable_anatop_clocks()
413 reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE | PFD3_CLKGATE; in disable_anatop_clocks()