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Searched refs:PHASE (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.h61 SRII(PHASE, DP_DTO, 0),\
62 SRII(PHASE, DP_DTO, 1),\
63 SRII(PHASE, DP_DTO, 2),\
64 SRII(PHASE, DP_DTO, 3),\
65 SRII(PHASE, DP_DTO, 4),\
66 SRII(PHASE, DP_DTO, 5),\
84 SRII(PHASE, DP_DTO, 0),\
85 SRII(PHASE, DP_DTO, 1),\
86 SRII(PHASE, DP_DTO, 2),\
87 SRII(PHASE, DP_DTO, 3),\
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Ddce_clock_source.c915 REG_WRITE(PHASE[inst], clock_100hz); in dce112_program_pix_clk()
994 clock_hz = REG_READ(PHASE[inst]); in get_pixel_clk_frequency_100hz()
/drivers/scsi/
DFlashPoint.c527 #define PHASE BIT(13) macro
1835 && !((RDW_HARPOON((ioport + hp_intstat)) & PHASE) in FlashPoint_HandleInterrupt()
1862 (PROG_HLT | RSEL | PHASE | BUS_FREE)); in FlashPoint_HandleInterrupt()
1898 (PHASE | IUNKWN | PROG_HLT)); in FlashPoint_HandleInterrupt()
2086 (PROG_HLT | TIMEOUT | SEL | BUS_FREE | PHASE | in FPT_SccbMgr_bad_isr()
2674 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_sres()
2679 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_sres()
2752 (PHASE | RESET)) in FPT_sres()
2834 while (!(RDW_HARPOON((port + hp_intstat)) & (PHASE | RESET)) && in FPT_sres()
2844 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_SendMsg()
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