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Searched refs:PIPEACONF_ENABLE (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/gma500/
Dmdfld_intel_display.c256 if ((temp & PIPEACONF_ENABLE) != 0) { in mdfld_disable_crtc()
257 temp &= ~PIPEACONF_ENABLE; in mdfld_disable_crtc()
270 & PIPEACONF_ENABLE)) || pipe == 1) { in mdfld_disable_crtc()
365 if ((temp & PIPEACONF_ENABLE) == 0) { in mdfld_crtc_dpms()
390 temp &= ~PIPEACONF_ENABLE; in mdfld_crtc_dpms()
406 temp |= PIPEACONF_ENABLE; in mdfld_crtc_dpms()
442 if ((temp & PIPEACONF_ENABLE) != 0) { in mdfld_crtc_dpms()
443 temp &= ~PIPEACONF_ENABLE; in mdfld_crtc_dpms()
455 | REG_READ(PIPECCONF)) & PIPEACONF_ENABLE)) in mdfld_crtc_dpms()
845 dev_priv->pipeconf[pipe] = PIPEACONF_ENABLE; /* FIXME_JLIU7 REG_READ(pipeconf_reg); */ in mdfld_crtc_mode_set()
Doaktrail_hdmi.c364 pipeconf |= PIPEACONF_ENABLE; in oaktrail_crtc_hdmi_mode_set()
404 if ((temp & PIPEACONF_ENABLE) != 0) { in oaktrail_crtc_hdmi_dpms()
405 REG_WRITE(PIPEBCONF, temp & ~PIPEACONF_ENABLE); in oaktrail_crtc_hdmi_dpms()
411 if ((temp & PIPEACONF_ENABLE) != 0) { in oaktrail_crtc_hdmi_dpms()
412 REG_WRITE(PCH_PIPEBCONF, temp & ~PIPEACONF_ENABLE); in oaktrail_crtc_hdmi_dpms()
446 if ((temp & PIPEACONF_ENABLE) == 0) { in oaktrail_crtc_hdmi_dpms()
447 REG_WRITE(PIPEBCONF, temp | PIPEACONF_ENABLE); in oaktrail_crtc_hdmi_dpms()
453 if ((temp & PIPEACONF_ENABLE) == 0) { in oaktrail_crtc_hdmi_dpms()
454 REG_WRITE(PCH_PIPEBCONF, temp | PIPEACONF_ENABLE); in oaktrail_crtc_hdmi_dpms()
Doaktrail_crtc.c262 if ((temp & PIPEACONF_ENABLE) == 0) { in oaktrail_crtc_dpms()
264 temp | PIPEACONF_ENABLE, i); in oaktrail_crtc_dpms()
306 if ((temp & PIPEACONF_ENABLE) != 0) { in oaktrail_crtc_dpms()
308 temp & ~PIPEACONF_ENABLE, i); in oaktrail_crtc_dpms()
Dgma_display.c244 if ((temp & PIPEACONF_ENABLE) == 0) in gma_crtc_dpms()
245 REG_WRITE(map->conf, temp | PIPEACONF_ENABLE); in gma_crtc_dpms()
290 if ((temp & PIPEACONF_ENABLE) != 0) { in gma_crtc_dpms()
291 REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE); in gma_crtc_dpms()
Dpsb_irq.c517 if (!(reg_val & PIPEACONF_ENABLE)) in psb_enable_vblank()
576 if (!(reg_val & PIPEACONF_ENABLE)) in mdfld_enable_te()
643 if (!(reg_val & PIPEACONF_ENABLE)) { in psb_get_vblank_counter()
Dpsb_intel_display.c202 pipeconf |= PIPEACONF_ENABLE; in psb_intel_crtc_mode_set()
Dpsb_intel_reg.h480 #define PIPEACONF_ENABLE (1 << 31) macro
Dcdv_intel_display.c724 pipeconf |= PIPEACONF_ENABLE; in cdv_intel_crtc_mode_set()