Searched refs:PLL_STATUS (Results 1 – 7 of 7) sorted by relevance
| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | pll.c | 19 #define PLL_STATUS 0x0004 macro
218 if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1) in dss_pll_wait_reset_done()
229 u32 v = readl_relaxed(pll->base + PLL_STATUS); in dss_wait_hsdiv_ack()
301 if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) { in dss_pll_write_config_type_a()
372 if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) { in dss_pll_write_config_type_b()
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| D | dsi.c | 1200 DSI_FLD_GET(PLL_STATUS, 0, 0), in _dsi_print_reset_status()
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| /drivers/gpu/drm/omapdrm/dss/ |
| D | pll.c | 19 #define PLL_STATUS 0x0004 macro
354 if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1) in dss_pll_wait_reset_done()
365 u32 v = readl_relaxed(pll->base + PLL_STATUS); in dss_wait_hsdiv_ack()
466 l = readl_relaxed(base + PLL_STATUS); in dss_pll_write_config_type_a()
488 if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) { in dss_pll_write_config_type_a()
560 if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) { in dss_pll_write_config_type_b()
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| D | dsi.c | 1153 DSI_FLD_GET(PLL_STATUS, 0, 0), in _dsi_print_reset_status()
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| /drivers/phy/ti/ |
| D | phy-ti-pipe3.c | 24 #define PLL_STATUS 0x00000004 macro
395 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); in ti_pipe3_dpll_wait_lock()
530 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); in ti_pipe3_init()
569 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); in ti_pipe3_exit()
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| /drivers/clk/pistachio/ |
| D | clk-pll.c | 16 #define PLL_STATUS 0x0 macro
90 while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK)) in pll_lock()
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| /drivers/clk/qcom/ |
| D | clk-alpha-pll.c | 55 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) macro
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