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Searched refs:PP_ON_DELAYS (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/gma500/
Dcdv_device.c286 regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS); in cdv_save_display_registers()
354 REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS); in cdv_restore_display_registers()
Dpsb_intel_reg.h184 #define PP_ON_DELAYS 0x61208 /* Cedartrail */ macro
Dcdv_intel_dp.c2080 pp_on = REG_READ(PP_ON_DELAYS); in cdv_intel_dp_init()
/drivers/gpu/drm/i915/display/
Dintel_lvds.c161 val = I915_READ(PP_ON_DELAYS(0)); in intel_lvds_pps_get_hw_state()
212 I915_WRITE(PP_ON_DELAYS(0), in intel_lvds_pps_init_hw()
Dintel_dp.c929 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & in vlv_initial_pps_pipe()
1036 regs->pp_on = PP_ON_DELAYS(pps_idx); in intel_pps_get_registers()
3490 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); in vlv_detach_power_sequencer()
Dintel_display.c1199 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; in assert_panel_unlocked()
1226 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; in assert_panel_unlocked()
/drivers/gpu/drm/i915/
Di915_reg.h4756 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) macro