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Searched refs:REG_A6XX_GMU_DCVS_PERF_SETTING (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/msm/adreno/
Da6xx_gmu.xml.h98 #define REG_A6XX_GMU_DCVS_PERF_SETTING 0x000023fd macro
Da6xx_gmu.c112 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, in __a6xx_gmu_set_freq()