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Searched refs:REG_GET_FIELD (Results 1 – 25 of 37) sorted by relevance

12

/drivers/gpu/drm/amd/amdgpu/
Dumc_v6_1.c101 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_1_query_correctable_error_count()
112 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_1_query_correctable_error_count()
120 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 && in umc_v6_1_query_correctable_error_count()
121 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v6_1_query_correctable_error_count()
122 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in umc_v6_1_query_correctable_error_count()
138 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in umc_v6_1_querry_uncorrectable_error_count()
139 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || in umc_v6_1_querry_uncorrectable_error_count()
140 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in umc_v6_1_querry_uncorrectable_error_count()
141 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v6_1_querry_uncorrectable_error_count()
142 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v6_1_querry_uncorrectable_error_count()
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Dsmu_v11_0_i2c.c144 } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0); in smu_v11_0_i2c_poll_tx_status()
152 if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) { in smu_v11_0_i2c_poll_tx_status()
157 if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_tx_status()
163 } else if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_tx_status()
187 if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_rx_status()
205 } while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0); in smu_v11_0_i2c_poll_rx_status()
255 if (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) { in smu_v11_0_i2c_transmit()
282 } while (numbytes && REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)); in smu_v11_0_i2c_transmit()
381 data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT); in smu_v11_0_i2c_receive()
428 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) && in smu_v11_0_i2c_activity_done()
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Dgfxhub_v1_1.c35 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); in gfxhub_v1_1_get_xgmi_info()
44 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); in gfxhub_v1_1_get_xgmi_info()
47 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD( in gfxhub_v1_1_get_xgmi_info()
Dgmc_v7_0.c97 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v7_0_mc_stop()
203 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v7_0_mc_load_microcode()
226 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
232 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
333 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v7_0_mc_init()
339 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v7_0_mc_init()
745 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v7_0_vm_decode_fault()
746 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
752 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
757 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
[all …]
Dgmc_v8_0.c185 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v8_0_mc_stop()
328 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v8_0_tonga_mc_load_microcode()
351 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
357 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
535 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v8_0_mc_init()
541 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v8_0_mc_init()
989 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v8_0_vm_decode_fault()
990 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
996 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
1001 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
[all …]
Dgmc_v10_0.c171 REG_GET_FIELD(status, in gmc_v10_0_process_interrupt()
174 REG_GET_FIELD(status, in gmc_v10_0_process_interrupt()
177 REG_GET_FIELD(status, in gmc_v10_0_process_interrupt()
180 REG_GET_FIELD(status, in gmc_v10_0_process_interrupt()
183 REG_GET_FIELD(status, in gmc_v10_0_process_interrupt()
668 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v10_0_get_vbios_fb_size()
676 size = (REG_GET_FIELD(viewport, in gmc_v10_0_get_vbios_fb_size()
678 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * in gmc_v10_0_get_vbios_fb_size()
Dgmc_v6_0.c82 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v6_0_mc_stop()
635 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v6_0_vm_decode_fault()
636 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
641 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
646 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
825 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v6_0_get_vbios_fb_size()
829 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * in gmc_v6_0_get_vbios_fb_size()
830 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * in gmc_v6_0_get_vbios_fb_size()
Dgmc_v9_0.c391 REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
394 REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
397 REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
400 REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
403 REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
1149 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v9_0_get_vbios_fb_size()
1158 size = (REG_GET_FIELD(viewport, in gmc_v9_0_get_vbios_fb_size()
1160 REG_GET_FIELD(viewport, in gmc_v9_0_get_vbios_fb_size()
1169 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * in gmc_v9_0_get_vbios_fb_size()
1170 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * in gmc_v9_0_get_vbios_fb_size()
Damdgpu_amdkfd_gfx_v7.c157 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, in get_tile_config()
159 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, in get_tile_config()
581 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { in kgd_hqd_destroy()
585 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { in kgd_hqd_destroy()
586 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) in kgd_hqd_destroy()
593 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) in kgd_hqd_destroy()
856 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in read_vmid_from_vmfault_reg()
Damdgpu_amdkfd_gfx_v10.c125 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, in amdgpu_amdkfd_get_tile_config()
127 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, in amdgpu_amdkfd_get_tile_config()
419 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_hqd_load()
681 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { in kgd_hqd_destroy()
685 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { in kgd_hqd_destroy()
686 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) in kgd_hqd_destroy()
693 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) in kgd_hqd_destroy()
Diceland_ih.c196 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in iceland_ih_get_wptr()
336 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in iceland_ih_is_idle()
351 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in iceland_ih_wait_for_idle()
Dcz_ih.c196 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in cz_ih_get_wptr()
336 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in cz_ih_is_idle()
351 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in cz_ih_wait_for_idle()
Damdgpu_amdkfd_gfx_v8.c112 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, in get_tile_config()
114 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, in get_tile_config()
577 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { in kgd_hqd_destroy()
581 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { in kgd_hqd_destroy()
582 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) in kgd_hqd_destroy()
589 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) in kgd_hqd_destroy()
Dgfx_v8_0.c1862 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); in gfx_v8_0_gpu_early_init()
1863 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); in gfx_v8_0_gpu_early_init()
1866 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); in gfx_v8_0_gpu_early_init()
1867 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); in gfx_v8_0_gpu_early_init()
1886 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS); in gfx_v8_0_gpu_early_init()
3484 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); in gfx_v8_0_get_rb_active_bitmap()
4887 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE) in gfx_v8_0_is_idle()
5001 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) in gfx_v8_0_check_soft_reset()
5005 if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) || in gfx_v8_0_check_soft_reset()
5006 REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) || in gfx_v8_0_check_soft_reset()
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Dtonga_ih.c198 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in tonga_ih_get_wptr()
347 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in tonga_ih_is_idle()
362 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in tonga_ih_wait_for_idle()
Dvi.c336 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK)) in vi_get_xclk()
340 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE)) in vi_get_xclk()
459 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER)) in vi_detect_hw_virtualization()
462 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE)) in vi_detect_hw_virtualization()
989 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); in vi_get_pcie_usage()
990 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); in vi_get_pcie_usage()
1019 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) && in vi_need_reset_on_init()
Dnavi10_ih.c217 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in navi10_ih_get_wptr()
222 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in navi10_ih_get_wptr()
Dgfx_v10_0.c1219 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
1226 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
1229 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
1232 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
1235 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
1728 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | in gfx_v10_0_get_tcc_info()
1729 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); in gfx_v10_0_get_tcc_info()
2258 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, in gfx_v10_0_rlc_backdoor_autoload_config_me_cache()
2295 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, in gfx_v10_0_rlc_backdoor_autoload_config_ce_cache()
2332 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, in gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache()
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Dsoc15.c845 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); in soc15_get_pcie_usage()
846 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); in soc15_get_pcie_usage()
894 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); in vega20_get_pcie_usage()
895 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); in vega20_get_pcie_usage()
Dsdma_v3_0.c1279 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || in sdma_v3_0_pre_soft_reset()
1280 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { in sdma_v3_0_pre_soft_reset()
1298 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || in sdma_v3_0_post_soft_reset()
1299 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { in sdma_v3_0_post_soft_reset()
Dvega10_ih.c380 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in vega10_ih_get_wptr()
395 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in vega10_ih_get_wptr()
Dcik.c1789 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); in cik_get_pcie_usage()
1790 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); in cik_get_pcie_usage()
1807 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) && in cik_need_reset_on_init()
Dgfx_v9_0.c1933 REG_GET_FIELD( in gfx_v9_0_gpu_early_init()
1942 REG_GET_FIELD( in gfx_v9_0_gpu_early_init()
1947 REG_GET_FIELD( in gfx_v9_0_gpu_early_init()
1952 REG_GET_FIELD( in gfx_v9_0_gpu_early_init()
1957 REG_GET_FIELD( in gfx_v9_0_gpu_early_init()
1962 REG_GET_FIELD( in gfx_v9_0_gpu_early_init()
3996 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), in gfx_v9_0_is_idle()
4043 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) in gfx_v9_0_soft_reset()
4558 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) in gfx_v9_0_set_safe_mode()
/drivers/gpu/drm/amd/powerplay/hwmgr/
Dvega10_thermal.c106 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), in vega10_fan_ctrl_get_fan_speed_rpm()
134 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
137 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
268 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega10_fan_ctrl_set_fan_speed_percent()
Dvega20_thermal.c150 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega20_fan_ctrl_set_fan_speed_percent()

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