1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2015 MediaTek Inc.
4 * Author: Tianping.Fang <tianping.fang@mediatek.com>
5 */
6
7 #include <linux/delay.h>
8 #include <linux/init.h>
9 #include <linux/module.h>
10 #include <linux/regmap.h>
11 #include <linux/rtc.h>
12 #include <linux/irqdomain.h>
13 #include <linux/platform_device.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/io.h>
17 #include <linux/mfd/mt6397/core.h>
18
19 #define RTC_BBPU 0x0000
20 #define RTC_BBPU_CBUSY BIT(6)
21
22 #define RTC_WRTGR 0x003c
23
24 #define RTC_IRQ_STA 0x0002
25 #define RTC_IRQ_STA_AL BIT(0)
26 #define RTC_IRQ_STA_LP BIT(3)
27
28 #define RTC_IRQ_EN 0x0004
29 #define RTC_IRQ_EN_AL BIT(0)
30 #define RTC_IRQ_EN_ONESHOT BIT(2)
31 #define RTC_IRQ_EN_LP BIT(3)
32 #define RTC_IRQ_EN_ONESHOT_AL (RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL)
33
34 #define RTC_AL_MASK 0x0008
35 #define RTC_AL_MASK_DOW BIT(4)
36
37 #define RTC_TC_SEC 0x000a
38 /* Min, Hour, Dom... register offset to RTC_TC_SEC */
39 #define RTC_OFFSET_SEC 0
40 #define RTC_OFFSET_MIN 1
41 #define RTC_OFFSET_HOUR 2
42 #define RTC_OFFSET_DOM 3
43 #define RTC_OFFSET_DOW 4
44 #define RTC_OFFSET_MTH 5
45 #define RTC_OFFSET_YEAR 6
46 #define RTC_OFFSET_COUNT 7
47
48 #define RTC_AL_SEC 0x0018
49
50 #define RTC_AL_SEC_MASK 0x003f
51 #define RTC_AL_MIN_MASK 0x003f
52 #define RTC_AL_HOU_MASK 0x001f
53 #define RTC_AL_DOM_MASK 0x001f
54 #define RTC_AL_DOW_MASK 0x0007
55 #define RTC_AL_MTH_MASK 0x000f
56 #define RTC_AL_YEA_MASK 0x007f
57
58 #define RTC_PDN2 0x002e
59 #define RTC_PDN2_PWRON_ALARM BIT(4)
60
61 #define RTC_MIN_YEAR 1968
62 #define RTC_BASE_YEAR 1900
63 #define RTC_NUM_YEARS 128
64 #define RTC_MIN_YEAR_OFFSET (RTC_MIN_YEAR - RTC_BASE_YEAR)
65
66 struct mt6397_rtc {
67 struct device *dev;
68 struct rtc_device *rtc_dev;
69 struct mutex lock;
70 struct regmap *regmap;
71 int irq;
72 u32 addr_base;
73 };
74
mtk_rtc_write_trigger(struct mt6397_rtc * rtc)75 static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc)
76 {
77 unsigned long timeout = jiffies + HZ;
78 int ret;
79 u32 data;
80
81 ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_WRTGR, 1);
82 if (ret < 0)
83 return ret;
84
85 while (1) {
86 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_BBPU,
87 &data);
88 if (ret < 0)
89 break;
90 if (!(data & RTC_BBPU_CBUSY))
91 break;
92 if (time_after(jiffies, timeout)) {
93 ret = -ETIMEDOUT;
94 break;
95 }
96 cpu_relax();
97 }
98
99 return ret;
100 }
101
mtk_rtc_irq_handler_thread(int irq,void * data)102 static irqreturn_t mtk_rtc_irq_handler_thread(int irq, void *data)
103 {
104 struct mt6397_rtc *rtc = data;
105 u32 irqsta, irqen;
106 int ret;
107
108 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_STA, &irqsta);
109 if ((ret >= 0) && (irqsta & RTC_IRQ_STA_AL)) {
110 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
111 irqen = irqsta & ~RTC_IRQ_EN_AL;
112 mutex_lock(&rtc->lock);
113 if (regmap_write(rtc->regmap, rtc->addr_base + RTC_IRQ_EN,
114 irqen) == 0)
115 mtk_rtc_write_trigger(rtc);
116 mutex_unlock(&rtc->lock);
117
118 return IRQ_HANDLED;
119 }
120
121 return IRQ_NONE;
122 }
123
__mtk_rtc_read_time(struct mt6397_rtc * rtc,struct rtc_time * tm,int * sec)124 static int __mtk_rtc_read_time(struct mt6397_rtc *rtc,
125 struct rtc_time *tm, int *sec)
126 {
127 int ret;
128 u16 data[RTC_OFFSET_COUNT];
129
130 mutex_lock(&rtc->lock);
131 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC,
132 data, RTC_OFFSET_COUNT);
133 if (ret < 0)
134 goto exit;
135
136 tm->tm_sec = data[RTC_OFFSET_SEC];
137 tm->tm_min = data[RTC_OFFSET_MIN];
138 tm->tm_hour = data[RTC_OFFSET_HOUR];
139 tm->tm_mday = data[RTC_OFFSET_DOM];
140 tm->tm_mon = data[RTC_OFFSET_MTH];
141 tm->tm_year = data[RTC_OFFSET_YEAR];
142
143 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, sec);
144 exit:
145 mutex_unlock(&rtc->lock);
146 return ret;
147 }
148
mtk_rtc_read_time(struct device * dev,struct rtc_time * tm)149 static int mtk_rtc_read_time(struct device *dev, struct rtc_time *tm)
150 {
151 time64_t time;
152 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
153 int days, sec, ret;
154
155 do {
156 ret = __mtk_rtc_read_time(rtc, tm, &sec);
157 if (ret < 0)
158 goto exit;
159 } while (sec < tm->tm_sec);
160
161 /* HW register use 7 bits to store year data, minus
162 * RTC_MIN_YEAR_OFFSET before write year data to register, and plus
163 * RTC_MIN_YEAR_OFFSET back after read year from register
164 */
165 tm->tm_year += RTC_MIN_YEAR_OFFSET;
166
167 /* HW register start mon from one, but tm_mon start from zero. */
168 tm->tm_mon--;
169 time = rtc_tm_to_time64(tm);
170
171 /* rtc_tm_to_time64 covert Gregorian date to seconds since
172 * 01-01-1970 00:00:00, and this date is Thursday.
173 */
174 days = div_s64(time, 86400);
175 tm->tm_wday = (days + 4) % 7;
176
177 exit:
178 return ret;
179 }
180
mtk_rtc_set_time(struct device * dev,struct rtc_time * tm)181 static int mtk_rtc_set_time(struct device *dev, struct rtc_time *tm)
182 {
183 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
184 int ret;
185 u16 data[RTC_OFFSET_COUNT];
186
187 tm->tm_year -= RTC_MIN_YEAR_OFFSET;
188 tm->tm_mon++;
189
190 data[RTC_OFFSET_SEC] = tm->tm_sec;
191 data[RTC_OFFSET_MIN] = tm->tm_min;
192 data[RTC_OFFSET_HOUR] = tm->tm_hour;
193 data[RTC_OFFSET_DOM] = tm->tm_mday;
194 data[RTC_OFFSET_MTH] = tm->tm_mon;
195 data[RTC_OFFSET_YEAR] = tm->tm_year;
196
197 mutex_lock(&rtc->lock);
198 ret = regmap_bulk_write(rtc->regmap, rtc->addr_base + RTC_TC_SEC,
199 data, RTC_OFFSET_COUNT);
200 if (ret < 0)
201 goto exit;
202
203 /* Time register write to hardware after call trigger function */
204 ret = mtk_rtc_write_trigger(rtc);
205
206 exit:
207 mutex_unlock(&rtc->lock);
208 return ret;
209 }
210
mtk_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alm)211 static int mtk_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
212 {
213 struct rtc_time *tm = &alm->time;
214 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
215 u32 irqen, pdn2;
216 int ret;
217 u16 data[RTC_OFFSET_COUNT];
218
219 mutex_lock(&rtc->lock);
220 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_EN, &irqen);
221 if (ret < 0)
222 goto err_exit;
223 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_PDN2, &pdn2);
224 if (ret < 0)
225 goto err_exit;
226
227 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC,
228 data, RTC_OFFSET_COUNT);
229 if (ret < 0)
230 goto err_exit;
231
232 alm->enabled = !!(irqen & RTC_IRQ_EN_AL);
233 alm->pending = !!(pdn2 & RTC_PDN2_PWRON_ALARM);
234 mutex_unlock(&rtc->lock);
235
236 tm->tm_sec = data[RTC_OFFSET_SEC] & RTC_AL_SEC_MASK;
237 tm->tm_min = data[RTC_OFFSET_MIN] & RTC_AL_MIN_MASK;
238 tm->tm_hour = data[RTC_OFFSET_HOUR] & RTC_AL_HOU_MASK;
239 tm->tm_mday = data[RTC_OFFSET_DOM] & RTC_AL_DOM_MASK;
240 tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_AL_MTH_MASK;
241 tm->tm_year = data[RTC_OFFSET_YEAR] & RTC_AL_YEA_MASK;
242
243 tm->tm_year += RTC_MIN_YEAR_OFFSET;
244 tm->tm_mon--;
245
246 return 0;
247 err_exit:
248 mutex_unlock(&rtc->lock);
249 return ret;
250 }
251
mtk_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alm)252 static int mtk_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
253 {
254 struct rtc_time *tm = &alm->time;
255 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
256 int ret;
257 u16 data[RTC_OFFSET_COUNT];
258
259 tm->tm_year -= RTC_MIN_YEAR_OFFSET;
260 tm->tm_mon++;
261
262 mutex_lock(&rtc->lock);
263 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC,
264 data, RTC_OFFSET_COUNT);
265 if (ret < 0)
266 goto exit;
267
268 data[RTC_OFFSET_SEC] = ((data[RTC_OFFSET_SEC] & ~(RTC_AL_SEC_MASK)) |
269 (tm->tm_sec & RTC_AL_SEC_MASK));
270 data[RTC_OFFSET_MIN] = ((data[RTC_OFFSET_MIN] & ~(RTC_AL_MIN_MASK)) |
271 (tm->tm_min & RTC_AL_MIN_MASK));
272 data[RTC_OFFSET_HOUR] = ((data[RTC_OFFSET_HOUR] & ~(RTC_AL_HOU_MASK)) |
273 (tm->tm_hour & RTC_AL_HOU_MASK));
274 data[RTC_OFFSET_DOM] = ((data[RTC_OFFSET_DOM] & ~(RTC_AL_DOM_MASK)) |
275 (tm->tm_mday & RTC_AL_DOM_MASK));
276 data[RTC_OFFSET_MTH] = ((data[RTC_OFFSET_MTH] & ~(RTC_AL_MTH_MASK)) |
277 (tm->tm_mon & RTC_AL_MTH_MASK));
278 data[RTC_OFFSET_YEAR] = ((data[RTC_OFFSET_YEAR] & ~(RTC_AL_YEA_MASK)) |
279 (tm->tm_year & RTC_AL_YEA_MASK));
280
281 if (alm->enabled) {
282 ret = regmap_bulk_write(rtc->regmap,
283 rtc->addr_base + RTC_AL_SEC,
284 data, RTC_OFFSET_COUNT);
285 if (ret < 0)
286 goto exit;
287 ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_AL_MASK,
288 RTC_AL_MASK_DOW);
289 if (ret < 0)
290 goto exit;
291 ret = regmap_update_bits(rtc->regmap,
292 rtc->addr_base + RTC_IRQ_EN,
293 RTC_IRQ_EN_ONESHOT_AL,
294 RTC_IRQ_EN_ONESHOT_AL);
295 if (ret < 0)
296 goto exit;
297 } else {
298 ret = regmap_update_bits(rtc->regmap,
299 rtc->addr_base + RTC_IRQ_EN,
300 RTC_IRQ_EN_ONESHOT_AL, 0);
301 if (ret < 0)
302 goto exit;
303 }
304
305 /* All alarm time register write to hardware after calling
306 * mtk_rtc_write_trigger. This can avoid race condition if alarm
307 * occur happen during writing alarm time register.
308 */
309 ret = mtk_rtc_write_trigger(rtc);
310 exit:
311 mutex_unlock(&rtc->lock);
312 return ret;
313 }
314
315 static const struct rtc_class_ops mtk_rtc_ops = {
316 .read_time = mtk_rtc_read_time,
317 .set_time = mtk_rtc_set_time,
318 .read_alarm = mtk_rtc_read_alarm,
319 .set_alarm = mtk_rtc_set_alarm,
320 };
321
mtk_rtc_probe(struct platform_device * pdev)322 static int mtk_rtc_probe(struct platform_device *pdev)
323 {
324 struct resource *res;
325 struct mt6397_chip *mt6397_chip = dev_get_drvdata(pdev->dev.parent);
326 struct mt6397_rtc *rtc;
327 int ret;
328
329 rtc = devm_kzalloc(&pdev->dev, sizeof(struct mt6397_rtc), GFP_KERNEL);
330 if (!rtc)
331 return -ENOMEM;
332
333 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
334 rtc->addr_base = res->start;
335
336 rtc->irq = platform_get_irq(pdev, 0);
337 if (rtc->irq < 0)
338 return rtc->irq;
339
340 rtc->regmap = mt6397_chip->regmap;
341 rtc->dev = &pdev->dev;
342 mutex_init(&rtc->lock);
343
344 platform_set_drvdata(pdev, rtc);
345
346 rtc->rtc_dev = devm_rtc_allocate_device(rtc->dev);
347 if (IS_ERR(rtc->rtc_dev))
348 return PTR_ERR(rtc->rtc_dev);
349
350 ret = request_threaded_irq(rtc->irq, NULL,
351 mtk_rtc_irq_handler_thread,
352 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
353 "mt6397-rtc", rtc);
354 if (ret) {
355 dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
356 rtc->irq, ret);
357 return ret;
358 }
359
360 device_init_wakeup(&pdev->dev, 1);
361
362 rtc->rtc_dev->ops = &mtk_rtc_ops;
363
364 ret = rtc_register_device(rtc->rtc_dev);
365 if (ret)
366 goto out_free_irq;
367
368 return 0;
369
370 out_free_irq:
371 free_irq(rtc->irq, rtc);
372 return ret;
373 }
374
mtk_rtc_remove(struct platform_device * pdev)375 static int mtk_rtc_remove(struct platform_device *pdev)
376 {
377 struct mt6397_rtc *rtc = platform_get_drvdata(pdev);
378
379 free_irq(rtc->irq, rtc);
380
381 return 0;
382 }
383
384 #ifdef CONFIG_PM_SLEEP
mt6397_rtc_suspend(struct device * dev)385 static int mt6397_rtc_suspend(struct device *dev)
386 {
387 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
388
389 if (device_may_wakeup(dev))
390 enable_irq_wake(rtc->irq);
391
392 return 0;
393 }
394
mt6397_rtc_resume(struct device * dev)395 static int mt6397_rtc_resume(struct device *dev)
396 {
397 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
398
399 if (device_may_wakeup(dev))
400 disable_irq_wake(rtc->irq);
401
402 return 0;
403 }
404 #endif
405
406 static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_rtc_suspend,
407 mt6397_rtc_resume);
408
409 static const struct of_device_id mt6397_rtc_of_match[] = {
410 { .compatible = "mediatek,mt6397-rtc", },
411 { }
412 };
413 MODULE_DEVICE_TABLE(of, mt6397_rtc_of_match);
414
415 static struct platform_driver mtk_rtc_driver = {
416 .driver = {
417 .name = "mt6397-rtc",
418 .of_match_table = mt6397_rtc_of_match,
419 .pm = &mt6397_pm_ops,
420 },
421 .probe = mtk_rtc_probe,
422 .remove = mtk_rtc_remove,
423 };
424
425 module_platform_driver(mtk_rtc_driver);
426
427 MODULE_LICENSE("GPL v2");
428 MODULE_AUTHOR("Tianping Fang <tianping.fang@mediatek.com>");
429 MODULE_DESCRIPTION("RTC Driver for MediaTek MT6397 PMIC");
430