1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __SMU_V11_0_H__ 24 #define __SMU_V11_0_H__ 25 26 #include "amdgpu_smu.h" 27 28 #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF 29 #define SMU11_DRIVER_IF_VERSION_VG20 0x13 30 #define SMU11_DRIVER_IF_VERSION_ARCT 0x09 31 #define SMU11_DRIVER_IF_VERSION_NV10 0x33 32 #define SMU11_DRIVER_IF_VERSION_NV14 0x34 33 34 /* MP Apertures */ 35 #define MP0_Public 0x03800000 36 #define MP0_SRAM 0x03900000 37 #define MP1_Public 0x03b00000 38 #define MP1_SRAM 0x03c00004 39 #define MP1_SMC_SIZE 0x40000 40 41 /* address block */ 42 #define smnMP1_FIRMWARE_FLAGS 0x3010024 43 #define smnMP0_FW_INTF 0x30101c0 44 #define smnMP1_PUB_CTRL 0x3010b14 45 46 #define TEMP_RANGE_MIN (0) 47 #define TEMP_RANGE_MAX (80 * 1000) 48 49 #define SMU11_TOOL_SIZE 0x19000 50 51 #define CLK_MAP(clk, index) \ 52 [SMU_##clk] = {1, (index)} 53 54 #define FEA_MAP(fea) \ 55 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT} 56 57 #define TAB_MAP(tab) \ 58 [SMU_TABLE_##tab] = {1, TABLE_##tab} 59 60 #define PWR_MAP(tab) \ 61 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab} 62 63 #define WORKLOAD_MAP(profile, workload) \ 64 [profile] = {1, (workload)} 65 66 static const struct smu_temperature_range smu11_thermal_policy[] = 67 { 68 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 69 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 70 }; 71 72 struct smu_11_0_cmn2aisc_mapping { 73 int valid_mapping; 74 int map_to; 75 }; 76 77 struct smu_11_0_max_sustainable_clocks { 78 uint32_t display_clock; 79 uint32_t phy_clock; 80 uint32_t pixel_clock; 81 uint32_t uclock; 82 uint32_t dcef_clock; 83 uint32_t soc_clock; 84 }; 85 86 struct smu_11_0_dpm_table { 87 uint32_t min; /* MHz */ 88 uint32_t max; /* MHz */ 89 }; 90 91 struct smu_11_0_dpm_tables { 92 struct smu_11_0_dpm_table soc_table; 93 struct smu_11_0_dpm_table gfx_table; 94 struct smu_11_0_dpm_table uclk_table; 95 struct smu_11_0_dpm_table eclk_table; 96 struct smu_11_0_dpm_table vclk_table; 97 struct smu_11_0_dpm_table dclk_table; 98 struct smu_11_0_dpm_table dcef_table; 99 struct smu_11_0_dpm_table pixel_table; 100 struct smu_11_0_dpm_table display_table; 101 struct smu_11_0_dpm_table phy_table; 102 struct smu_11_0_dpm_table fclk_table; 103 }; 104 105 struct smu_11_0_dpm_context { 106 struct smu_11_0_dpm_tables dpm_tables; 107 uint32_t workload_policy_mask; 108 uint32_t dcef_min_ds_clk; 109 }; 110 111 enum smu_11_0_power_state { 112 SMU_11_0_POWER_STATE__D0 = 0, 113 SMU_11_0_POWER_STATE__D1, 114 SMU_11_0_POWER_STATE__D3, /* Sleep*/ 115 SMU_11_0_POWER_STATE__D4, /* Hibernate*/ 116 SMU_11_0_POWER_STATE__D5, /* Power off*/ 117 }; 118 119 struct smu_11_0_power_context { 120 uint32_t power_source; 121 uint8_t in_power_limit_boost_mode; 122 enum smu_11_0_power_state power_state; 123 }; 124 125 enum smu_v11_0_baco_seq { 126 BACO_SEQ_BACO = 0, 127 BACO_SEQ_MSR, 128 BACO_SEQ_BAMACO, 129 BACO_SEQ_ULPS, 130 BACO_SEQ_COUNT, 131 }; 132 133 void smu_v11_0_set_smu_funcs(struct smu_context *smu); 134 135 #endif 136