/drivers/gpu/drm/amd/display/dc/dce/ |
D | dce_link_encoder.h | 40 SRI(AUX_CONTROL, DP_AUX, id), \ 41 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id) 44 SRI(DC_HPD_CONTROL, HPD, id) 51 SRI(DIG_BE_CNTL, DIG, id), \ 52 SRI(DIG_BE_EN_CNTL, DIG, id), \ 53 SRI(DP_CONFIG, DP, id), \ 54 SRI(DP_DPHY_CNTL, DP, id), \ 55 SRI(DP_DPHY_PRBS_CNTL, DP, id), \ 56 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\ 57 SRI(DP_DPHY_SYM0, DP, id), \ [all …]
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D | dce_transform.h | 39 SRI(LB_DATA_FORMAT, LB, id), \ 40 SRI(GAMUT_REMAP_CONTROL, DCP, id), \ 41 SRI(GAMUT_REMAP_C11_C12, DCP, id), \ 42 SRI(GAMUT_REMAP_C13_C14, DCP, id), \ 43 SRI(GAMUT_REMAP_C21_C22, DCP, id), \ 44 SRI(GAMUT_REMAP_C23_C24, DCP, id), \ 45 SRI(GAMUT_REMAP_C31_C32, DCP, id), \ 46 SRI(GAMUT_REMAP_C33_C34, DCP, id), \ 47 SRI(OUTPUT_CSC_C11_C12, DCP, id), \ 48 SRI(OUTPUT_CSC_C13_C14, DCP, id), \ [all …]
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D | dce_stream_encoder.h | 44 SRI(AFMT_AVI_INFO0, DIG, id), \ 45 SRI(AFMT_AVI_INFO1, DIG, id), \ 46 SRI(AFMT_AVI_INFO2, DIG, id), \ 47 SRI(AFMT_AVI_INFO3, DIG, id) 50 SRI(AFMT_GENERIC_0, DIG, id), \ 51 SRI(AFMT_GENERIC_1, DIG, id), \ 52 SRI(AFMT_GENERIC_2, DIG, id), \ 53 SRI(AFMT_GENERIC_3, DIG, id), \ 54 SRI(AFMT_GENERIC_4, DIG, id), \ 55 SRI(AFMT_GENERIC_5, DIG, id), \ [all …]
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D | dce_aux.h | 34 SRI(AUX_CONTROL, DP_AUX, id), \ 35 SRI(AUX_ARB_CONTROL, DP_AUX, id), \ 36 SRI(AUX_SW_DATA, DP_AUX, id), \ 37 SRI(AUX_SW_CONTROL, DP_AUX, id), \ 38 SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \ 39 SRI(AUX_SW_STATUS, DP_AUX, id) 43 SRI(AUX_CONTROL, DP_AUX, id), \ 44 SRI(AUX_ARB_CONTROL, DP_AUX, id), \ 45 SRI(AUX_SW_DATA, DP_AUX, id), \ 46 SRI(AUX_SW_CONTROL, DP_AUX, id), \ [all …]
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D | dce_ipp.h | 35 SRI(CUR_UPDATE, DCP, id), \ 36 SRI(CUR_CONTROL, DCP, id), \ 37 SRI(CUR_POSITION, DCP, id), \ 38 SRI(CUR_HOT_SPOT, DCP, id), \ 39 SRI(CUR_COLOR1, DCP, id), \ 40 SRI(CUR_COLOR2, DCP, id), \ 41 SRI(CUR_SIZE, DCP, id), \ 42 SRI(CUR_SURFACE_ADDRESS_HIGH, DCP, id), \ 43 SRI(CUR_SURFACE_ADDRESS, DCP, id), \ 44 SRI(PRESCALE_GRPH_CONTROL, DCP, id), \ [all …]
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D | dce_opp.h | 44 SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ 45 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 46 SRI(FMT_CONTROL, FMT, id), \ 47 SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \ 48 SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \ 49 SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \ 50 SRI(FMT_CLAMP_CNTL, FMT, id), \ 51 SRI(FMT_CLAMP_COMPONENT_R, FMT, id), \ 52 SRI(FMT_CLAMP_COMPONENT_G, FMT, id), \ 53 SRI(FMT_CLAMP_COMPONENT_B, FMT, id) [all …]
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D | dce_mem_input.h | 35 SRI(GRPH_ENABLE, DCP, id),\ 36 SRI(GRPH_CONTROL, DCP, id),\ 37 SRI(GRPH_X_START, DCP, id),\ 38 SRI(GRPH_Y_START, DCP, id),\ 39 SRI(GRPH_X_END, DCP, id),\ 40 SRI(GRPH_Y_END, DCP, id),\ 41 SRI(GRPH_PITCH, DCP, id),\ 42 SRI(HW_ROTATION, DCP, id),\ 43 SRI(GRPH_SWAP_CNTL, DCP, id),\ 44 SRI(PRESCALE_GRPH_CONTROL, DCP, id),\ [all …]
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D | dce_abm.h | 58 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ 59 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ 60 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ 61 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ 62 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ 63 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ 64 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ 65 SRI(BL1_PWM_USER_LEVEL, ABM, id), \ 66 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ 67 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
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D | dce_clock_source.h | 34 SRI(RESYNC_CNTL, PIXCLK, id), \ 35 SRI(PLL_CNTL, BPHYC_PLL, id) 38 SRI(RESYNC_CNTL, PIXCLK, id), \ 39 SRI(PLL_CNTL, DCCG_PLL, id) 42 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id) 60 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 83 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 109 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
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/drivers/gpu/drm/amd/display/dc/dcn20/ |
D | dcn20_dpp.h | 35 SRI(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM, id), \ 36 SRI(CM_BLNDGAM_CONTROL, CM, id), \ 37 SRI(CM_BLNDGAM_RAMB_START_CNTL_B, CM, id), \ 38 SRI(CM_BLNDGAM_RAMB_START_CNTL_G, CM, id), \ 39 SRI(CM_BLNDGAM_RAMB_START_CNTL_R, CM, id), \ 40 SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM, id), \ 41 SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM, id), \ 42 SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM, id), \ 43 SRI(CM_BLNDGAM_RAMB_END_CNTL1_B, CM, id), \ 44 SRI(CM_BLNDGAM_RAMB_END_CNTL2_B, CM, id), \ [all …]
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D | dcn20_mmhubbub.h | 43 #define SRI(reg_name, block, id)\ macro 60 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\ 61 SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\ 62 SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\ 63 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\ 64 SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\ 65 SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\ 66 SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\ 67 SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\ 68 SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\ [all …]
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D | dcn20_hubp.h | 37 SRI(PREFETCH_SETTINGS, HUBPREQ, id),\ 38 SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\ 39 SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),\ 40 SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),\ 41 SRI(CURSOR_SETTINGS, HUBPREQ, id), \ 42 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \ 43 SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \ 44 SRI(CURSOR_SIZE, CURSOR0_, id), \ 45 SRI(CURSOR_CONTROL, CURSOR0_, id), \ 46 SRI(CURSOR_POSITION, CURSOR0_, id), \ [all …]
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D | dcn20_dsc.h | 36 SRI(DSC_TOP_CONTROL, DSC_TOP, id),\ 37 SRI(DSC_DEBUG_CONTROL, DSC_TOP, id),\ 38 SRI(DSCC_CONFIG0, DSCC, id),\ 39 SRI(DSCC_CONFIG1, DSCC, id),\ 40 SRI(DSCC_STATUS, DSCC, id),\ 41 SRI(DSCC_INTERRUPT_CONTROL_STATUS, DSCC, id),\ 42 SRI(DSCC_PPS_CONFIG0, DSCC, id),\ 43 SRI(DSCC_PPS_CONFIG1, DSCC, id),\ 44 SRI(DSCC_PPS_CONFIG2, DSCC, id),\ 45 SRI(DSCC_PPS_CONFIG3, DSCC, id),\ [all …]
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D | dcn20_optc.h | 33 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\ 34 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\ 35 SRI(OTG_GSL_WINDOW_X, OTG, inst),\ 36 SRI(OTG_GSL_WINDOW_Y, OTG, inst),\ 37 SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\ 38 SRI(OTG_DSC_START_POSITION, OTG, inst),\ 39 SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\ 40 SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\ 41 SRI(OPTC_WIDTH_CONTROL, ODM, inst),\ 42 SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ [all …]
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D | dcn20_vmid.h | 37 #define SRI(reg_name, block, id)\ macro 45 SRI(CNTL, DCN_VM_CONTEXT, id),\ 46 SRI(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id),\ 47 SRI(PAGE_TABLE_BASE_ADDR_LO32, DCN_VM_CONTEXT, id),\ 48 SRI(PAGE_TABLE_START_ADDR_HI32, DCN_VM_CONTEXT, id),\ 49 SRI(PAGE_TABLE_START_ADDR_LO32, DCN_VM_CONTEXT, id),\ 50 SRI(PAGE_TABLE_END_ADDR_HI32, DCN_VM_CONTEXT, id),\ 51 SRI(PAGE_TABLE_END_ADDR_LO32, DCN_VM_CONTEXT, id)
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D | dcn20_opp.h | 37 SRI(DPG_CONTROL, DPG, id), \ 38 SRI(DPG_DIMENSIONS, DPG, id), \ 39 SRI(DPG_COLOUR_B_CB, DPG, id), \ 40 SRI(DPG_COLOUR_G_Y, DPG, id), \ 41 SRI(DPG_COLOUR_R_CR, DPG, id), \ 42 SRI(DPG_RAMP_CONTROL, DPG, id), \ 43 SRI(DPG_STATUS, DPG, id) 48 SRI(FMT_422_CONTROL, FMT, id), \ 49 SRI(OPPBUF_CONTROL1, OPPBUF, id)
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D | dcn20_stream_encoder.h | 35 SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \ 36 SRI(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \ 37 SRI(DP_DSC_CNTL, DP, id), \ 38 SRI(DP_DSC_BYTES_PER_PIXEL, DP, id), \ 39 SRI(DME_CONTROL, DIG, id),\ 40 SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \ 41 SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ 42 SRI(DP_SEC_FRAMING4, DP, id)
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/drivers/gpu/drm/amd/display/dc/dcn10/ |
D | dcn10_hubp.h | 35 SRI(DCHUBP_CNTL, HUBP, id),\ 36 SRI(HUBPREQ_DEBUG_DB, HUBP, id),\ 37 SRI(HUBPREQ_DEBUG, HUBP, id),\ 38 SRI(DCSURF_ADDR_CONFIG, HUBP, id),\ 39 SRI(DCSURF_TILING_CONFIG, HUBP, id),\ 40 SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\ 41 SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\ 42 SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\ 43 SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\ 44 SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \ [all …]
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D | dcn10_stream_encoder.h | 35 SRI(AFMT_CNTL, DIG, id), \ 36 SRI(AFMT_GENERIC_0, DIG, id), \ 37 SRI(AFMT_GENERIC_1, DIG, id), \ 38 SRI(AFMT_GENERIC_2, DIG, id), \ 39 SRI(AFMT_GENERIC_3, DIG, id), \ 40 SRI(AFMT_GENERIC_4, DIG, id), \ 41 SRI(AFMT_GENERIC_5, DIG, id), \ 42 SRI(AFMT_GENERIC_6, DIG, id), \ 43 SRI(AFMT_GENERIC_7, DIG, id), \ 44 SRI(AFMT_GENERIC_HDR, DIG, id), \ [all …]
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D | dcn10_dwb.h | 40 #define SRI(reg_name, block, id)\ macro 54 SRI(WB_ENABLE, CNV, inst),\ 55 SRI(WB_EC_CONFIG, CNV, inst),\ 56 SRI(CNV_MODE, CNV, inst),\ 57 SRI(WB_SOFT_RESET, CNV, inst),\ 58 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\ 59 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\ 60 SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\ 61 SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\ 62 SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\ [all …]
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D | dcn10_dpp.h | 45 SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\ 46 SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\ 47 SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\ 48 SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\ 49 SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\ 50 SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\ 51 SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\ 52 SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \ 53 SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \ 54 SRI(OTG_H_BLANK, DSCL, id), \ [all …]
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D | dcn10_optc.h | 35 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\ 36 SRI(OTG_VUPDATE_PARAM, OTG, inst),\ 37 SRI(OTG_VREADY_PARAM, OTG, inst),\ 38 SRI(OTG_BLANK_CONTROL, OTG, inst),\ 39 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\ 40 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\ 41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\ 42 SRI(OTG_H_TOTAL, OTG, inst),\ 43 SRI(OTG_H_BLANK_START_END, OTG, inst),\ 44 SRI(OTG_H_SYNC_A, OTG, inst),\ [all …]
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D | dcn10_ipp.h | 35 SRI(FORMAT_CONTROL, CNVC_CFG, id), \ 36 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \ 37 SRI(CURSOR0_CONTROL, CNVC_CUR, id), \ 38 SRI(CURSOR0_COLOR0, CNVC_CUR, id), \ 39 SRI(CURSOR0_COLOR1, CNVC_CUR, id) 43 SRI(CURSOR_SETTINS, HUBPREQ, id), \ 44 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \ 45 SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \ 46 SRI(CURSOR_SIZE, CURSOR, id), \ 47 SRI(CURSOR_CONTROL, CURSOR, id), \ [all …]
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D | dcn10_link_encoder.h | 36 SRI(AUX_CONTROL, DP_AUX, id), \ 37 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id) 40 SRI(DC_HPD_CONTROL, HPD, id) 43 SRI(DIG_BE_CNTL, DIG, id), \ 44 SRI(DIG_BE_EN_CNTL, DIG, id), \ 45 SRI(TMDS_CTL_BITS, DIG, id), \ 46 SRI(DP_CONFIG, DP, id), \ 47 SRI(DP_DPHY_CNTL, DP, id), \ 48 SRI(DP_DPHY_PRBS_CNTL, DP, id), \ 49 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\ [all …]
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D | dcn10_opp.h | 37 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 38 SRI(FMT_CONTROL, FMT, id), \ 39 SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \ 40 SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \ 41 SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \ 42 SRI(FMT_CLAMP_CNTL, FMT, id), \ 43 SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ 44 SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id), \ 45 SRI(OPPBUF_CONTROL, OPPBUF, id),\ 46 SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, id), \ [all …]
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