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Searched refs:SSPP_VIG0 (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
112 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
195 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
290 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
357 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
Dmdp5_ctl.c290 case SSPP_VIG0: return MDP5_CTL_LAYER_REG_VIG0(stage); in mdp_ctl_blend_mask()
313 case SSPP_VIG0: return MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3; in mdp_ctl_blend_ext_mask()
441 case SSPP_VIG0: return MDP5_CTL_FLUSH_VIG0; in mdp_ctl_flush_mask_pipe()
Dmdp5.xml.h69 SSPP_VIG0 = 1, enumerator
539 case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]); in __offset_PIPE()
Dmdp5_kms.c831 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, in hwpipe_init() enumerator
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_plane.c185 plane->base.id, pdpu->pipe - SSPP_VIG0, in _dpu_plane_calc_fill_level()
250 trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0, in _dpu_plane_set_qos_lut()
256 pdpu->pipe - SSPP_VIG0, in _dpu_plane_set_qos_lut()
301 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, in _dpu_plane_set_danger_lut()
309 pdpu->pipe - SSPP_VIG0, in _dpu_plane_set_danger_lut()
353 pdpu->pipe - SSPP_VIG0, in _dpu_plane_set_qos_ctrl()
404 qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0; in _dpu_plane_set_qos_remap()
Ddpu_hw_top.c139 status->sspp[SSPP_VIG0] = (value >> 4) & 0x3; in dpu_hw_get_danger_status()
236 status->sspp[SSPP_VIG0] = (value >> 4) & 0x1; in dpu_hw_get_safe_status()
Ddpu_hw_ctl.c121 case SSPP_VIG0: in dpu_hw_ctl_get_bitmask_sspp()
326 case SSPP_VIG0: in dpu_hw_ctl_setup_blendstage()
Ddpu_hw_mdss.h108 SSPP_VIG0, enumerator
Ddpu_hw_interrupts.c374 { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG0, DPU_INTR_HIST_VIG_0_DONE, 2},
375 { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG0,
Ddpu_hw_catalog.c188 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK,
Ddpu_kms.c99 for (i = SSPP_VIG0; i < SSPP_MAX; i++) in _dpu_danger_signal_status()
100 seq_printf(s, "SSPP%d : 0x%x \t", i - SSPP_VIG0, in _dpu_danger_signal_status()
Ddpu_crtc.c146 dpu_plane_pipe(plane) - SSPP_VIG0, in _dpu_crtc_blend_setup_mixer()
162 dpu_plane_pipe(plane) - SSPP_VIG0, in _dpu_crtc_blend_setup_mixer()