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Searched refs:TCR (Results 1 – 25 of 26) sorted by relevance

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/drivers/clocksource/
Dtimer-keystone.c24 #define TCR 0x20 macro
79 tcr = keystone_timer_readl(TCR); in keystone_timer_config()
86 keystone_timer_writel(off, TCR); in keystone_timer_config()
102 keystone_timer_writel(tcr, TCR); in keystone_timer_config()
110 tcr = keystone_timer_readl(TCR); in keystone_timer_disable()
114 keystone_timer_writel(tcr, TCR); in keystone_timer_disable()
178 keystone_timer_writel(0, TCR); in keystone_timer_init()
Dh8300_tpu.c19 #define TCR 0x0 macro
90 iowrite8(0x0f, p->mapbase1 + TCR); in tpu_clocksource_enable()
91 iowrite8(0x03, p->mapbase2 + TCR); in tpu_clocksource_enable()
103 iowrite8(0, p->mapbase1 + TCR); in tpu_clocksource_disable()
104 iowrite8(0, p->mapbase2 + TCR); in tpu_clocksource_disable()
Dsh_tmu.c69 #define TCR 2 /* channel register */ macro
95 if (reg_nr == TCR) in sh_tmu_read()
117 if (reg_nr == TCR) in sh_tmu_write()
160 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); in __sh_tmu_enable()
185 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); in __sh_tmu_disable()
212 sh_tmu_read(ch, TCR); in sh_tmu_set_next()
215 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); in sh_tmu_set_next()
235 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); in sh_tmu_interrupt()
237 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); in sh_tmu_interrupt()
Dh8300_timer16.c20 #define TCR 0 macro
95 iowrite8(0x83, p->mapbase + TCR); in timer16_enable()
Dsh_mtu2.c52 #define TCR 0 /* channel register */ macro
143 [TCR] = 0,
227 sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64); in sh_mtu2_enable()
/drivers/staging/rtl8712/
Dhal_init.c199 tmp16 = r8712_read16(adapter, TCR); in rtl8712_dl_fw()
202 tmp16 = r8712_read16(adapter, TCR); in rtl8712_dl_fw()
228 tmp16 = r8712_read16(adapter, TCR); in rtl8712_dl_fw()
231 tmp16 = r8712_read16(adapter, TCR); in rtl8712_dl_fw()
250 r8712_read32(adapter, TCR); in rtl8712_dl_fw()
254 tmp16 = r8712_read16(adapter, TCR); in rtl8712_dl_fw()
257 tmp16 = r8712_read16(adapter, TCR); in rtl8712_dl_fw()
279 tmp16 = r8712_read16(adapter, TCR); in rtl8712_dl_fw()
282 tmp16 = r8712_read16(adapter, TCR); in rtl8712_dl_fw()
295 tmp16 = r8712_read16(adapter, TCR); in rtl8712_dl_fw()
[all …]
Drtl8712_cmdctrl_regdef.h12 #define TCR (RTL8712_CMDCTRL_ + 0x0004) macro
Dusb_halinit.c264 val8 = r8712_read8(adapter, TCR); in r8712_usb_hal_bus_init()
/drivers/watchdog/
Ddavinci_wdt.c36 #define TCR (0x20) macro
80 iowrite32(0, davinci_wdt->base + TCR); in davinci_wdt_start()
94 iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR); in davinci_wdt_start()
149 iowrite32(0, davinci_wdt->base + TCR); in davinci_wdt_restart()
/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
Dfw.c40 cpustatus = rtl_read_byte(rtlpriv, TCR); in _rtl92s_firmware_enable_cpu()
207 cpustatus = rtl_read_byte(rtlpriv, TCR); in _rtl92s_firmware_checkready()
224 cpustatus = rtl_read_byte(rtlpriv, TCR); in _rtl92s_firmware_checkready()
247 cpustatus = rtl_read_byte(rtlpriv, TCR); in _rtl92s_firmware_checkready()
267 cpustatus = rtl_read_byte(rtlpriv, TCR); in _rtl92s_firmware_checkready()
286 tmpu4b = rtl_read_dword(rtlpriv, TCR); in _rtl92s_firmware_checkready()
287 rtl_write_dword(rtlpriv, TCR, (tmpu4b & (~TCR_ICV))); in _rtl92s_firmware_checkready()
Dhw.c574 rtl_write_byte(rtlpriv, TCR, 0); in _rtl92se_macconfig_before_fwdownload()
714 tmpu1b = rtl_read_byte(rtlpriv, TCR); in _rtl92se_macconfig_before_fwdownload()
761 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) | in _rtl92se_macconfig_after_fwdownload()
1179 temp = rtl_read_dword(rtlpriv, TCR); in _rtl92se_set_media_status()
1180 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8))); in _rtl92se_set_media_status()
1181 rtl_write_dword(rtlpriv, TCR, temp | BIT(8)); in _rtl92se_set_media_status()
1422 rtl_write_byte(rtlpriv, TCR, 0); in _rtl92se_power_domain_init()
Dreg.h36 #define TCR 0x0044 macro
/drivers/net/ethernet/smsc/
Dsmc91c92_cs.c149 #define TCR 0 /* transmit control register */ macro
1098 mask_bits(0xff00, ioaddr + TCR); in smc_close()
1294 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR); in smc_tx_err()
1329 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR); in smc_eph_irq()
1653 outw(TCR_CLEAR, ioaddr + TCR); in smc_reset()
1682 TCR_ENABLE | TCR_PAD_EN | smc->duplex, ioaddr + TCR); in smc_reset()
1788 outw(inw(ioaddr + TCR) | smc->duplex, ioaddr + TCR); in media_check()
1863 tmp = inw(ioaddr + TCR); in smc_netdev_get_ecmd()
1890 tmp = inw(ioaddr + TCR); in smc_netdev_set_ecmd()
1895 outw(tmp, ioaddr + TCR); in smc_netdev_set_ecmd()
Dsmc9194.c332 outw( TCR_CLEAR, ioaddr + TCR ); in smc_reset()
363 outw( TCR_NORMAL, ioaddr + TCR ); in smc_enable()
394 outb( TCR_CLEAR, ioaddr + TCR ); in smc_shutdown()
1284 outw( inw( ioaddr + TCR ) | TCR_ENABLE, ioaddr + TCR ); in smc_tx()
Dsmc9194.h64 #define TCR 0 /* transmit control register */ macro
/drivers/tty/
Dsynclink_gt.c394 #define TCR 0x82 /* tx control */ macro
1385 value = rd_reg16(info, TCR); in set_break()
1390 wr_reg16(info, TCR, value); in set_break()
2268 unsigned short val = rd_reg16(info, TCR); in isr_txeom()
2269 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in isr_txeom()
2270 wr_reg16(info, TCR, val); /* clear reset bit */ in isr_txeom()
2853 val = rd_reg16(info, TCR); in set_interface()
2858 wr_reg16(info, TCR, val); in set_interface()
4010 wr_reg16(info, TCR, in tx_start()
4011 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); in tx_start()
[all …]
/drivers/dma/sh/
Dshdmac.c40 #define TCR 0x08 /* Transfer Count Register */ macro
219 sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR); in dmae_set_reg()
423 (sh_dmae_readl(sh_chan, TCR) << sh_chan->xmit_shift); in sh_dmae_get_partial()
/drivers/net/ethernet/via/
Dvia-velocity.c932 BYTE_REG_BITS_OFF(TCR_TB2BDIS, &regs->TCR); in velocity_set_media_mode()
938 BYTE_REG_BITS_ON(TCR_TB2BDIS, &regs->TCR); in velocity_set_media_mode()
1831 BYTE_REG_BITS_ON(TCR_TB2BDIS, &regs->TCR); in velocity_error()
1833 BYTE_REG_BITS_OFF(TCR_TB2BDIS, &regs->TCR); in velocity_error()
2544 td_ptr->tdesc1.TCR = TCR0_TIC; in velocity_xmit()
2578 td_ptr->tdesc1.TCR |= TCR0_VETAG; in velocity_xmit()
2587 td_ptr->tdesc1.TCR |= TCR0_TCPCK; in velocity_xmit()
2589 td_ptr->tdesc1.TCR |= (TCR0_UDPCK); in velocity_xmit()
2590 td_ptr->tdesc1.TCR |= TCR0_IPCK; in velocity_xmit()
Dvia-velocity.h200 u8 TCR; member
971 volatile u8 TCR; member
/drivers/net/ethernet/amd/
Dariadne.h381 volatile u_char TCR; /* Timer Control Register */ member
/drivers/net/wan/
Dhd64572.h103 #define TCR 0x152 /* Tx DMA Critical Request Reg */ macro
Dhd64572.c456 sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */ in sca_open()
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h128 TCR = 0x040, enumerator
/drivers/net/usb/
Drtl8150.c24 #define TCR 0x012f macro
642 set_registers(dev, TCR, 1, &tcr); in enable_net_traffic()
/drivers/spi/
Dspi-atmel.c905 spi_writel(as, TCR, len); in atmel_spi_pdc_next_xfer()
1327 spi_readl(as, TCR), spi_readl(as, RCR)); in atmel_spi_one_transfer()
1336 spi_writel(as, TCR, 0); in atmel_spi_one_transfer()

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