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Searched refs:VBLANK_ACK (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dsi_enums.h28 #define VBLANK_ACK (1 << 4) macro
Dsid.h817 # define VBLANK_ACK (1 << 4) macro
Ddce_v6_0.c2940 WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); in dce_v6_0_crtc_irq()
Ddce_v11_0.c3316 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); in dce_v11_0_crtc_vblank_int_ack()
Ddce_v10_0.c3190 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); in dce_v10_0_crtc_vblank_int_ack()
/drivers/gpu/drm/radeon/
Dsid.h813 # define VBLANK_ACK (1 << 4) macro
Dcik.c7336 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7340 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7352 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7356 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7369 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7373 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
Dcikd.h884 # define VBLANK_ACK (1 << 4) macro
Devergreend.h1278 # define VBLANK_ACK (1 << 4) macro
Devergreen.c4637 VBLANK_ACK); in evergreen_irq_ack()
Dsi.c6171 VBLANK_ACK); in si_irq_ack()