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Searched refs:VC5_OUT_DIV_INT (Results 1 – 1 of 1) sorted by relevance

/drivers/clk/
Dclk-versaclock5.c86 #define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n)) macro
479 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0), in vc5_fod_recalc_rate()