Home
last modified time | relevance | path

Searched refs:VM_L2_CNTL (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfxhub_v1_0.c141 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
142 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gfxhub_v1_0_init_cache_regs()
144 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, in gfxhub_v1_0_init_cache_regs()
146 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); in gfxhub_v1_0_init_cache_regs()
147 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gfxhub_v1_0_init_cache_regs()
148 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); in gfxhub_v1_0_init_cache_regs()
310 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v1_0_gart_disable()
Dmmhub_v1_0.c170 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
171 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in mmhub_v1_0_init_cache_regs()
173 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, in mmhub_v1_0_init_cache_regs()
175 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); in mmhub_v1_0_init_cache_regs()
176 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in mmhub_v1_0_init_cache_regs()
177 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); in mmhub_v1_0_init_cache_regs()
357 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v1_0_gart_disable()
Dgmc_v7_0.c608 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
609 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gmc_v7_0_gart_enable()
610 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
611 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
612 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); in gmc_v7_0_gart_enable()
613 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gmc_v7_0_gart_enable()
614 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); in gmc_v7_0_gart_enable()
727 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v7_0_gart_disable()
Dgmc_v8_0.c835 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
836 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gmc_v8_0_gart_enable()
837 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()
838 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()
839 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); in gmc_v8_0_gart_enable()
840 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gmc_v8_0_gart_enable()
841 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); in gmc_v8_0_gart_enable()
971 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v8_0_gart_disable()
Dsid.h371 #define VM_L2_CNTL 0x500 macro
/drivers/gpu/drm/radeon/
Drv770.c910 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
957 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_disable()
987 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_agp_enable()
Drv770d.h642 #define VM_L2_CNTL 0x1400 macro
Dnid.h104 #define VM_L2_CNTL 0x1400 macro
Dni.c1294 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in cayman_pcie_gart_enable()
1375 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_disable()
Dsid.h369 #define VM_L2_CNTL 0x1400 macro
Dcikd.h487 #define VM_L2_CNTL 0x1400 macro
Dr600.c1143 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_pcie_gart_enable()
1197 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in r600_pcie_gart_disable()
1235 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_agp_enable()
Devergreen.c2410 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_pcie_gart_enable()
2464 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_pcie_gart_disable()
2493 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_agp_enable()
Devergreend.h1150 #define VM_L2_CNTL 0x1400 macro
Dr600d.h587 #define VM_L2_CNTL 0x1400 macro
Dsi.c4305 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in si_pcie_gart_enable()
4393 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_disable()
Dcik.c5453 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in cik_pcie_gart_enable()
5570 WREG32(VM_L2_CNTL, in cik_pcie_gart_disable()