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Searched refs:VM_L2_CNTL3 (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfxhub_v1_0.c158 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v1_0_init_cache_regs()
159 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in gfxhub_v1_0_init_cache_regs()
162 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v1_0_init_cache_regs()
163 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in gfxhub_v1_0_init_cache_regs()
Dmmhub_v1_0.c186 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v1_0_init_cache_regs()
187 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in mmhub_v1_0_init_cache_regs()
190 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v1_0_init_cache_regs()
191 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in mmhub_v1_0_init_cache_regs()
Dgmc_v7_0.c622 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); in gmc_v7_0_gart_enable()
623 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v7_0_gart_enable()
624 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); in gmc_v7_0_gart_enable()
Dgmc_v8_0.c850 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); in gmc_v8_0_gart_enable()
851 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v8_0_gart_enable()
852 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); in gmc_v8_0_gart_enable()
Dsid.h387 #define VM_L2_CNTL3 0x502 macro
/drivers/gpu/drm/radeon/
Drv770.c914 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_enable()
960 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_disable()
991 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_agp_enable()
Drv770d.h650 #define VM_L2_CNTL3 0x1408 macro
Dnid.h120 #define VM_L2_CNTL3 0x1408 macro
Dni.c1301 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cayman_pcie_gart_enable()
1380 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cayman_pcie_gart_disable()
Dsid.h385 #define VM_L2_CNTL3 0x1408 macro
Dcikd.h503 #define VM_L2_CNTL3 0x1408 macro
Dr600.c1147 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_pcie_gart_enable()
1199 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_pcie_gart_disable()
1239 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_agp_enable()
Devergreen.c2414 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_enable()
2467 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_disable()
2497 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_agp_enable()
Devergreend.h1158 #define VM_L2_CNTL3 0x1408 macro
Dr600d.h595 #define VM_L2_CNTL3 0x1408 macro
Dsi.c4312 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in si_pcie_gart_enable()
4398 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in si_pcie_gart_disable()
Dcik.c5460 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_enable()
5577 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_disable()