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Searched refs:WREG32_IDX (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/radeon/
Dradeon_cursor.c68 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset, in radeon_hide_cursor()
72 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, in radeon_hide_cursor()
86 WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN); in radeon_hide_cursor()
Dradeon_combios.c3254 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef); in combios_detect_ram()
Dradeon.h2517 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) macro
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_cgs.c92 return WREG32_IDX(index, value); in amdgpu_cgs_write_ind_register()
Damdgpu.h1068 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) macro
Ddce_v8_0.c2190 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v8_0_hide_cursor()
2205 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v8_0_show_cursor()
Ddce_v6_0.c2177 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_hide_cursor()
2194 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
Ddce_v11_0.c2369 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_hide_cursor()
2386 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_show_cursor()
Ddce_v10_0.c2290 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_hide_cursor()
2307 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_show_cursor()