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Searched refs:WREG32_OR (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/radeon/
Dr600_hdmi.c231 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset, in r600_set_avi_packet()
234 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, in r600_set_avi_packet()
345 WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset, in r600_set_vbi_packet()
366 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, in r600_set_audio_packet()
399 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE); in r600_set_mute()
453 WREG32_OR(HDMI0_CONTROL + offset, in r600_hdmi_update_audio_settings()
461 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, in r600_hdmi_update_audio_settings()
487 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); in r600_hdmi_enable()
495 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); in r600_hdmi_enable()
503 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); in r600_hdmi_enable()
Ddce3_1_afmt.c215 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, in dce3_2_set_audio_packet()
219 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset, in dce3_2_set_audio_packet()
229 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE); in dce3_2_set_mute()
Devergreen_hdmi.c384 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, in dce4_set_audio_packet()
395 WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE); in dce4_set_mute()
419 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_hdmi_enable()
458 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_dp_enable()
Devergreen.c1750 WREG32_OR(DC_HPDx_INT_CONTROL(hpd), DC_HPDx_INT_POLARITY); in evergreen_hpd_set_polarity()
4646 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_ACK); in evergreen_irq_ack()
4651 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_RX_INT_ACK); in evergreen_irq_ack()
4656 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i], in evergreen_irq_ack()
Dsi.c6180 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_ACK); in si_irq_ack()
6185 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_RX_INT_ACK); in si_irq_ack()
Dradeon.h2550 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) macro
/drivers/gpu/drm/amd/amdgpu/
Dvce_v3_0.c538 WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000); in vce_v3_0_mc_resume()
Damdgpu.h1097 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) macro
Ddce_v8_0.c1640 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset, in dce_v8_0_afmt_setmode()
1648 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset, in dce_v8_0_afmt_setmode()
/drivers/misc/habanalabs/
Dhabanalabs.h1047 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) macro
/drivers/misc/habanalabs/goya/
Dgoya.c535 WREG32_OR(reg, asid); in goya_mmu_prepare_reg()
1131 WREG32_OR(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset, in _goya_tpc_mbist_workaround()
1146 WREG32_OR(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset, in _goya_tpc_mbist_workaround()