| /drivers/watchdog/ |
| D | ar7_wdt.c | 46 #define WRITE_REG(x, v) writel((v), (void __iomem *)&(x)) macro
75 WRITE_REG(ar7_wdt->kick_lock, 0x5555); in ar7_wdt_kick()
77 WRITE_REG(ar7_wdt->kick_lock, 0xaaaa); in ar7_wdt_kick()
79 WRITE_REG(ar7_wdt->kick, value); in ar7_wdt_kick()
88 WRITE_REG(ar7_wdt->prescale_lock, 0x5a5a); in ar7_wdt_prescale()
90 WRITE_REG(ar7_wdt->prescale_lock, 0xa5a5); in ar7_wdt_prescale()
92 WRITE_REG(ar7_wdt->prescale, value); in ar7_wdt_prescale()
101 WRITE_REG(ar7_wdt->change_lock, 0x6666); in ar7_wdt_change()
103 WRITE_REG(ar7_wdt->change_lock, 0xbbbb); in ar7_wdt_change()
105 WRITE_REG(ar7_wdt->change, value); in ar7_wdt_change()
[all …]
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| /drivers/net/ethernet/tehuti/ |
| D | tehuti.c | 132 do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
134 do { WRITE_REG(priv, regIMR, 0); } while (0)
171 WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type)); in bdx_fifo_init()
172 WRITE_REG(priv, reg_CFG1, H32_64(f->da)); in bdx_fifo_init()
343 WRITE_REG(priv, regINIT_SEMAPHORE, 1); in bdx_fw_load()
371 WRITE_REG(priv, regUNC_MAC2_A, val); in bdx_restore_mac()
373 WRITE_REG(priv, regUNC_MAC1_A, val); in bdx_restore_mac()
375 WRITE_REG(priv, regUNC_MAC0_A, val); in bdx_restore_mac()
396 WRITE_REG(priv, regFRM_LENGTH, 0X3FE0); in bdx_hw_start()
397 WRITE_REG(priv, regPAUSE_QUANT, 0x96); in bdx_hw_start()
[all …]
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| D | tehuti.h | 98 #define WRITE_REG(pp, reg, val) writel(val, pp->pBdxRegs + reg) macro
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| /drivers/parisc/ |
| D | sba_iommu.c | 135 #define WRITE_REG(value, addr) WRITE_REG64(value, addr) macro
138 #define WRITE_REG(value, addr) WRITE_REG32(value, addr) macro
661 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM); in sba_mark_invalid()
1311 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); in sba_ioc_init_pluto()
1324 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK); in sba_ioc_init_pluto()
1345 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG); in sba_ioc_init_pluto()
1351 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE); in sba_ioc_init_pluto()
1357 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM); in sba_ioc_init_pluto()
1473 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE); in sba_ioc_init()
1474 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK); in sba_ioc_init()
[all …]
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| D | lba_pci.c | 932 WRITE_REG##size(val, astro_iop_base + addr); \
990 WRITE_REG##size(val, where); \
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| /drivers/ide/ |
| D | opti621.c | 25 #define WRITE_REG 1 /* index of Write cycle timing register */ macro
118 write_reg(tim, WRITE_REG); in opti621_set_pio_mode()
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| /drivers/ata/ |
| D | pata_opti.c | 40 WRITE_REG = 1, /* index of Write cycle timing register */ enumerator
144 opti_write_reg(ap, data_rec_timing[clock][pio], WRITE_REG); in opti_set_piomode()
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| D | pata_optidma.c | 39 WRITE_REG = 1, /* index of Write cycle timing register */ enumerator
170 iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG); in optidma_mode_setup()
173 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG); in optidma_mode_setup()
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| /drivers/staging/rts5208/ |
| D | ms.c | 728 retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, in ms_switch_parallel_bus()
748 retval = ms_write_bytes(chip, WRITE_REG, 1, in ms_switch_8bit_bus()
1277 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
1361 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE),
1411 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
1488 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 7);
1540 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
1691 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
1798 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE),
1846 retval = ms_write_bytes(chip, WRITE_REG, 7,
[all …]
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| D | ms.h | 40 #define WRITE_REG 0x0B macro
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| /drivers/staging/rtl8712/ |
| D | rtl871x_mp_ioctl.h | 336 GEN_MP_IOCTL_SUBCODE(WRITE_REG),
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| /drivers/staging/rtl8723bs/include/ |
| D | rtw_mp.h | 168 WRITE_REG = 1, enumerator
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