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Searched refs:amdgpu_ring_emit_wreg (Results 1 – 18 of 18) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgmc_v10_0.c389 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), in gmc_v10_0_emit_flush_gpu_tlb()
392 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), in gmc_v10_0_emit_flush_gpu_tlb()
406 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0); in gmc_v10_0_emit_flush_gpu_tlb()
422 amdgpu_ring_emit_wreg(ring, reg, pasid); in gmc_v10_0_emit_pasid_mapping()
Dgmc_v9_0.c589 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), in gmc_v9_0_emit_flush_gpu_tlb()
592 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), in gmc_v9_0_emit_flush_gpu_tlb()
605 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0); in gmc_v9_0_emit_flush_gpu_tlb()
625 amdgpu_ring_emit_wreg(ring, reg, pasid); in gmc_v9_0_emit_pasid_mapping()
Dnbio_v6_1.c61 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in nbio_v6_1_hdp_flush()
Dnbio_v2_3.c61 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in nbio_v2_3_hdp_flush()
Dnbio_v7_0.c69 …amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> … in nbio_v7_0_hdp_flush()
Dgmc_v7_0.c452 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); in gmc_v7_0_emit_flush_gpu_tlb()
455 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v7_0_emit_flush_gpu_tlb()
463 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); in gmc_v7_0_emit_pasid_mapping()
Dnbio_v7_4.c86 …amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> … in nbio_v7_4_hdp_flush()
Dgmc_v6_0.c381 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); in gmc_v6_0_emit_flush_gpu_tlb()
384 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v6_0_emit_flush_gpu_tlb()
Damdgpu_virt.c106 amdgpu_ring_emit_wreg(ring, reg, v); in amdgpu_virt_kiq_wreg()
Damdgpu_ring.c395 amdgpu_ring_emit_wreg(ring, reg0, ref); in amdgpu_ring_emit_reg_write_reg_wait_helper()
Dgmc_v8_0.c654 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); in gmc_v8_0_emit_flush_gpu_tlb()
657 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v8_0_emit_flush_gpu_tlb()
665 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); in gmc_v8_0_emit_pasid_mapping()
Damdgpu_ring.h247 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) macro
Dcik.c1730 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); in cik_flush_hdp()
1741 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); in cik_invalidate_hdp()
Dvi.c915 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); in vi_flush_hdp()
926 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); in vi_invalidate_hdp()
Dsi.c1248 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); in si_flush_hdp()
1259 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); in si_invalidate_hdp()
Dnv.c499 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in nv_invalidate_hdp()
Dsoc15.c797 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in soc15_invalidate_hdp()
Dsdma_v5_0.c1180 amdgpu_ring_emit_wreg(ring, reg0, ref); in sdma_v5_0_ring_emit_reg_write_reg_wait()