| /drivers/gpio/ |
| D | gpio-omap.c | 75 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
81 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) argument
106 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
109 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
115 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_reg() argument
118 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
122 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg()
123 bank->context.dataout |= l; in omap_set_gpio_dataout_reg()
125 reg += bank->regs->clr_dataout; in omap_set_gpio_dataout_reg()
126 bank->context.dataout &= ~l; in omap_set_gpio_dataout_reg()
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| D | gpio-brcmstb.c | 36 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument
37 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument
38 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument
39 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument
40 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument
41 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument
42 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument
43 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) argument
44 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) argument
76 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_gc_to_priv() local
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| D | gpio-tegra.c | 62 unsigned int bank; member
107 static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port, in tegra_gpio_compose() argument
110 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); in tegra_gpio_compose()
225 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; in tegra_gpio_set_debounce() local
242 spin_lock_irqsave(&bank->dbc_lock[port], flags); in tegra_gpio_set_debounce()
243 if (bank->dbc_cnt[port] < debounce_ms) { in tegra_gpio_set_debounce()
245 bank->dbc_cnt[port] = debounce_ms; in tegra_gpio_set_debounce()
247 spin_unlock_irqrestore(&bank->dbc_lock[port], flags); in tegra_gpio_set_debounce()
275 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); in tegra_gpio_irq_ack() local
276 struct tegra_gpio_info *tgi = bank->tgi; in tegra_gpio_irq_ack()
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| D | gpio-f7188x.c | 67 struct f7188x_gpio_bank *bank; member
240 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); in f7188x_gpio_get_direction() local
241 struct f7188x_sio *sio = bank->data->sio; in f7188x_gpio_get_direction()
249 dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); in f7188x_gpio_get_direction()
259 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); in f7188x_gpio_direction_in() local
260 struct f7188x_sio *sio = bank->data->sio; in f7188x_gpio_direction_in()
268 dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); in f7188x_gpio_direction_in()
270 superio_outb(sio->addr, gpio_dir(bank->regbase), dir); in f7188x_gpio_direction_in()
280 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); in f7188x_gpio_get() local
281 struct f7188x_sio *sio = bank->data->sio; in f7188x_gpio_get()
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| D | sgpio-aspeed.c | 90 const struct aspeed_sgpio_bank *bank, in bank_reg() argument
95 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
97 return gpio->base + bank->rdata_reg; in bank_reg()
99 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
101 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
103 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
105 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
107 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in bank_reg()
120 unsigned int bank = GPIO_BANK(offset); in to_bank() local
122 WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks)); in to_bank()
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| D | gpio-aspeed.c | 32 unsigned int bank; member
209 const struct aspeed_gpio_bank *bank, in bank_reg() argument
214 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
216 return gpio->base + bank->rdata_reg; in bank_reg()
218 return gpio->base + bank->val_regs + GPIO_VAL_DIR; in bank_reg()
220 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
222 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
224 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
226 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
228 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in bank_reg()
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| D | gpio-adp5588.c | 68 unsigned bank = ADP5588_BANK(off); in adp5588_gpio_get_value() local
74 if (dev->dir[bank] & bit) in adp5588_gpio_get_value()
75 val = dev->dat_out[bank]; in adp5588_gpio_get_value()
77 val = adp5588_gpio_read(dev->client, GPIO_DAT_STAT1 + bank); in adp5588_gpio_get_value()
87 unsigned bank, bit; in adp5588_gpio_set_value() local
90 bank = ADP5588_BANK(off); in adp5588_gpio_set_value()
95 dev->dat_out[bank] |= bit; in adp5588_gpio_set_value()
97 dev->dat_out[bank] &= ~bit; in adp5588_gpio_set_value()
99 adp5588_gpio_write(dev->client, GPIO_DAT_OUT1 + bank, in adp5588_gpio_set_value()
100 dev->dat_out[bank]); in adp5588_gpio_set_value()
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| /drivers/pinctrl/sh-pfc/ |
| D | sh_pfc.h | 444 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
445 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
446 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument
448 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
449 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
450 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
451 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
452 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
453 #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) argument
455 #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \ argument
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| /drivers/pinctrl/samsung/ |
| D | pinctrl-exynos.c | 54 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
55 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
59 spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
61 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
63 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
65 spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask()
72 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_ack() local
73 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; in exynos_irq_ack()
75 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); in exynos_irq_ack()
82 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_unmask() local
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| D | pinctrl-samsung.c | 359 struct samsung_pin_bank **bank) in pin_to_reg_bank() argument
371 if (bank) in pin_to_reg_bank()
372 *bank = b; in pin_to_reg_bank()
381 struct samsung_pin_bank *bank; in samsung_pinmux_setup() local
393 ®, &pin_offset, &bank); in samsung_pinmux_setup()
394 type = bank->type; in samsung_pinmux_setup()
403 spin_lock_irqsave(&bank->slock, flags); in samsung_pinmux_setup()
410 spin_unlock_irqrestore(&bank->slock, flags); in samsung_pinmux_setup()
436 struct samsung_pin_bank *bank; in samsung_pinconf_rw() local
445 &pin_offset, &bank); in samsung_pinconf_rw()
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| D | pinctrl-s3c24xx.c | 101 struct samsung_pin_bank *bank; member
139 struct samsung_pin_bank *bank, int pin) in s3c24xx_eint_set_function() argument
141 const struct samsung_pin_bank_type *bank_type = bank->type; in s3c24xx_eint_set_function()
149 reg = d->virt_base + bank->pctl_offset; in s3c24xx_eint_set_function()
153 spin_lock_irqsave(&bank->slock, flags); in s3c24xx_eint_set_function()
157 val |= bank->eint_func << shift; in s3c24xx_eint_set_function()
160 spin_unlock_irqrestore(&bank->slock, flags); in s3c24xx_eint_set_function()
165 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); in s3c24xx_eint_type() local
166 struct samsung_pinctrl_drv_data *d = bank->drvdata; in s3c24xx_eint_type()
167 int index = bank->eint_offset + data->hwirq; in s3c24xx_eint_type()
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| D | pinctrl-s3c64xx.c | 213 struct samsung_pin_bank *bank; member
268 struct samsung_pin_bank *bank, int pin) in s3c64xx_irq_set_function() argument
270 const struct samsung_pin_bank_type *bank_type = bank->type; in s3c64xx_irq_set_function()
278 reg = d->virt_base + bank->pctl_offset; in s3c64xx_irq_set_function()
289 spin_lock_irqsave(&bank->slock, flags); in s3c64xx_irq_set_function()
293 val |= bank->eint_func << shift; in s3c64xx_irq_set_function()
296 spin_unlock_irqrestore(&bank->slock, flags); in s3c64xx_irq_set_function()
305 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in s3c64xx_gpio_irq_set_mask() local
306 struct samsung_pinctrl_drv_data *d = bank->drvdata; in s3c64xx_gpio_irq_set_mask()
307 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; in s3c64xx_gpio_irq_set_mask()
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| /drivers/crypto/qat/qat_common/ |
| D | adf_transport.c | 80 static int adf_reserve_ring(struct adf_etr_bank_data *bank, uint32_t ring) in adf_reserve_ring() argument
82 spin_lock(&bank->lock); in adf_reserve_ring()
83 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring()
84 spin_unlock(&bank->lock); in adf_reserve_ring()
87 bank->ring_mask |= (1 << ring); in adf_reserve_ring()
88 spin_unlock(&bank->lock); in adf_reserve_ring()
92 static void adf_unreserve_ring(struct adf_etr_bank_data *bank, uint32_t ring) in adf_unreserve_ring() argument
94 spin_lock(&bank->lock); in adf_unreserve_ring()
95 bank->ring_mask &= ~(1 << ring); in adf_unreserve_ring()
96 spin_unlock(&bank->lock); in adf_unreserve_ring()
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| D | adf_transport_access_macros.h | 121 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
122 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
124 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
125 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
127 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
128 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
130 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
131 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
133 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
138 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
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| D | adf_transport_debug.c | 88 struct adf_etr_bank_data *bank = ring->bank; in adf_ring_show() local
89 void __iomem *csr = ring->bank->csr_addr; in adf_ring_show()
94 head = READ_CSR_RING_HEAD(csr, bank->bank_number, in adf_ring_show()
96 tail = READ_CSR_RING_TAIL(csr, bank->bank_number, in adf_ring_show()
98 empty = READ_CSR_E_STAT(csr, bank->bank_number); in adf_ring_show()
104 ring->ring_number, ring->bank->bank_number); in adf_ring_show()
164 ring->bank->bank_debug_dir, in adf_ring_debugfs_add()
201 struct adf_etr_bank_data *bank = sfile->private; in adf_bank_show() local
205 bank->bank_number); in adf_bank_show()
208 struct adf_etr_ring_data *ring = &bank->rings[ring_id]; in adf_bank_show()
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| /drivers/pinctrl/stm32/ |
| D | pinctrl-stm32.c | 151 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument
154 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
155 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
158 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument
161 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
163 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
164 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode()
167 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_driving() argument
170 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); in stm32_gpio_backup_driving()
171 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; in stm32_gpio_backup_driving()
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| /drivers/pinctrl/ |
| D | pinctrl-rockchip.c | 342 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
345 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
348 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
681 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, in rockchip_get_recalced_mux() argument
684 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
691 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
1112 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, in rockchip_get_mux_route() argument
1115 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
1122 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1137 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) in rockchip_get_mux() argument
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| D | pinctrl-oxnas.c | 30 #define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK) argument
71 unsigned int bank; member
275 .bank = _pin / PINS_PER_BANK, \
601 fname, pg->bank, pg->pin, in oxnas_ox810se_pinmux_enable()
605 (pg->bank ? in oxnas_ox810se_pinmux_enable()
612 (pg->bank ? in oxnas_ox810se_pinmux_enable()
619 (pg->bank ? in oxnas_ox810se_pinmux_enable()
645 unsigned int offset = (pg->bank ? PINMUX_820_BANK_OFFSET : 0); in oxnas_ox820_pinmux_enable()
652 fname, pg->bank, pg->pin, in oxnas_ox820_pinmux_enable()
697 struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc); in oxnas_ox810se_gpio_request_enable() local
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| /drivers/bus/ |
| D | uniphier-system-bus.c | 35 struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS]; member
39 int bank, u32 addr, u64 paddr, u32 size) in uniphier_system_bus_add_bank() argument
45 bank, addr, paddr, size); in uniphier_system_bus_add_bank()
47 if (bank >= ARRAY_SIZE(priv->bank)) { in uniphier_system_bus_add_bank()
48 dev_err(priv->dev, "unsupported bank number %d\n", bank); in uniphier_system_bus_add_bank()
52 if (priv->bank[bank].base || priv->bank[bank].end) { in uniphier_system_bus_add_bank()
54 "range for bank %d has already been specified\n", bank); in uniphier_system_bus_add_bank()
86 priv->bank[bank].base = paddr; in uniphier_system_bus_add_bank()
87 priv->bank[bank].end = end; in uniphier_system_bus_add_bank()
90 bank, priv->bank[bank].base, priv->bank[bank].end); in uniphier_system_bus_add_bank()
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| /drivers/dma/ipu/ |
| D | ipu_irq.c | 72 struct ipu_irq_bank *bank; member
96 struct ipu_irq_bank *bank; in ipu_irq_unmask() local
102 bank = map->bank; in ipu_irq_unmask()
103 if (!bank) { in ipu_irq_unmask()
109 reg = ipu_read_reg(bank->ipu, bank->control); in ipu_irq_unmask()
111 ipu_write_reg(bank->ipu, reg, bank->control); in ipu_irq_unmask()
119 struct ipu_irq_bank *bank; in ipu_irq_mask() local
125 bank = map->bank; in ipu_irq_mask()
126 if (!bank) { in ipu_irq_mask()
132 reg = ipu_read_reg(bank->ipu, bank->control); in ipu_irq_mask()
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| /drivers/pinctrl/sunxi/ |
| D | pinctrl-sunxi.h | 32 #define SUNXI_PINCTRL_PIN(bank, pin) \ argument
33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
237 u8 bank = pin / PINS_PER_BANK; in sunxi_mux_reg() local
238 u32 offset = bank * BANK_MEM_SIZE; in sunxi_mux_reg()
252 u8 bank = pin / PINS_PER_BANK; in sunxi_data_reg() local
253 u32 offset = bank * BANK_MEM_SIZE; in sunxi_data_reg()
267 u8 bank = pin / PINS_PER_BANK; in sunxi_dlevel_reg() local
268 u32 offset = bank * BANK_MEM_SIZE; in sunxi_dlevel_reg()
282 u8 bank = pin / PINS_PER_BANK; in sunxi_pull_reg() local
283 u32 offset = bank * BANK_MEM_SIZE; in sunxi_pull_reg()
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| /drivers/leds/ |
| D | leds-tca6507.c | 171 struct bank { struct
176 } bank[3]; member
187 int bank; /* Bank used, or -1 */ member
293 static void set_code(struct tca6507_chip *tca, int reg, int bank, int new) in set_code() argument
297 if (bank) { in set_code()
310 static void set_level(struct tca6507_chip *tca, int bank, int level) in set_level() argument
312 switch (bank) { in set_level()
315 set_code(tca, TCA6507_MAX_INTENSITY, bank, level); in set_level()
321 tca->bank[bank].level = level; in set_level()
325 static void set_times(struct tca6507_chip *tca, int bank) in set_times() argument
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| /drivers/hwspinlock/ |
| D | hwspinlock_core.c | 132 ret = hwlock->bank->ops->trylock(hwlock); in __hwspin_trylock()
238 if (hwlock->bank->ops->relax) in __hwspin_lock_timeout()
239 hwlock->bank->ops->relax(hwlock); in __hwspin_lock_timeout()
284 hwlock->bank->ops->unlock(hwlock); in __hwspin_unlock()
370 if (hwlock->bank->dev->of_node == args.np) { in of_hwspin_lock_get_id()
380 if (id < 0 || id >= hwlock->bank->num_locks) { in of_hwspin_lock_get_id()
384 id += hwlock->bank->base_id; in of_hwspin_lock_get_id()
486 int hwspin_lock_register(struct hwspinlock_device *bank, struct device *dev, in hwspin_lock_register() argument
492 if (!bank || !ops || !dev || !num_locks || !ops->trylock || in hwspin_lock_register()
498 bank->dev = dev; in hwspin_lock_register()
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| /drivers/pinctrl/sirf/ |
| D | pinctrl-sirf.c | 424 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); in sirfsoc_gpio_irq_ack() local
429 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); in sirfsoc_gpio_irq_ack()
441 struct sirfsoc_gpio_bank *bank, in __sirfsoc_gpio_irq_mask() argument
447 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); in __sirfsoc_gpio_irq_mask()
463 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); in sirfsoc_gpio_irq_mask() local
465 __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); in sirfsoc_gpio_irq_mask()
472 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); in sirfsoc_gpio_irq_unmask() local
477 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); in sirfsoc_gpio_irq_unmask()
493 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); in sirfsoc_gpio_irq_type() local
498 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); in sirfsoc_gpio_irq_type()
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| /drivers/memory/ |
| D | jz4780-nemc.c | 69 unsigned int bank, count = 0; in jz4780_nemc_num_banks() local
74 bank = of_read_number(prop, 1); in jz4780_nemc_num_banks()
75 if (!(referenced & BIT(bank))) { in jz4780_nemc_num_banks()
76 referenced |= BIT(bank); in jz4780_nemc_num_banks()
91 void jz4780_nemc_set_type(struct device *dev, unsigned int bank, in jz4780_nemc_set_type() argument
102 nfcsr &= ~(NEMC_NFCSR_TNFEn(bank) | NEMC_NFCSR_NFEn(bank)); in jz4780_nemc_set_type()
105 nfcsr &= ~NEMC_NFCSR_TNFEn(bank); in jz4780_nemc_set_type()
106 nfcsr |= NEMC_NFCSR_NFEn(bank); in jz4780_nemc_set_type()
123 void jz4780_nemc_assert(struct device *dev, unsigned int bank, bool assert) in jz4780_nemc_assert() argument
131 nfcsr |= NEMC_NFCSR_NFCEn(bank); in jz4780_nemc_assert()
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