| /drivers/net/wireless/zydas/zd1211rw/ |
| D | zd_rf_rf2959.c | 32 static int bits(u32 rw, int from, int to)
41 return bits(rw, bit, bit);
46 int reg = bits(rw, 18, 22);
47 int rw_flag = bits(rw, 23, 23);
54 bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1),
63 bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0, 3));
67 bits(rw, 6, 17), bits(rw, 0, 5));
70 PDEBUG("reg3 IFPLL3 num %d", bits(rw, 0, 17));
74 bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
82 bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0,3));
[all …]
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| /drivers/video/fbdev/core/ |
| D | syscopyarea.c | 29 const unsigned long *src, unsigned src_idx, int bits, unsigned n) in bitcpy() argument
36 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); in bitcpy()
40 if (dst_idx+n <= bits) { in bitcpy()
52 n -= bits - dst_idx; in bitcpy()
56 n /= bits; in bitcpy()
80 right = shift & (bits - 1); in bitcpy()
81 left = -shift & (bits - 1); in bitcpy()
83 if (dst_idx+n <= bits) { in bitcpy()
90 } else if (src_idx+n <= bits) { in bitcpy()
114 n -= bits - dst_idx; in bitcpy()
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| D | cfbcopyarea.c | 47 const unsigned long __iomem *src, unsigned src_idx, int bits, in bitcpy() argument
58 memmove((char *)dst + ((dst_idx & (bits - 1))) / 8, in bitcpy()
59 (char *)src + ((src_idx & (bits - 1))) / 8, n / 8); in bitcpy()
64 last = ~fb_shifted_pixels_mask_long(p, (dst_idx+n) % bits, bswapmask); in bitcpy()
69 if (dst_idx+n <= bits) { in bitcpy()
82 n -= bits - dst_idx; in bitcpy()
86 n /= bits; in bitcpy()
110 int const left = shift & (bits - 1); in bitcpy()
111 int const right = -shift & (bits - 1); in bitcpy()
113 if (dst_idx+n <= bits) { in bitcpy()
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| D | sysfillrect.c | 26 unsigned long pat, unsigned n, int bits) in bitfill_aligned() argument
34 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); in bitfill_aligned()
36 if (dst_idx+n <= bits) { in bitfill_aligned()
48 n -= bits - dst_idx; in bitfill_aligned()
52 n /= bits; in bitfill_aligned()
82 unsigned long pat, int left, int right, unsigned n, int bits) in bitfill_unaligned() argument
90 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); in bitfill_unaligned()
92 if (dst_idx+n <= bits) { in bitfill_unaligned()
104 n -= bits - dst_idx; in bitfill_unaligned()
108 n /= bits; in bitfill_unaligned()
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| D | cfbfillrect.c | 36 unsigned long pat, unsigned n, int bits, u32 bswapmask) in bitfill_aligned() argument
44 last = ~fb_shifted_pixels_mask_long(p, (dst_idx+n) % bits, bswapmask); in bitfill_aligned()
46 if (dst_idx+n <= bits) { in bitfill_aligned()
58 n -= bits - dst_idx; in bitfill_aligned()
62 n /= bits; in bitfill_aligned()
93 unsigned long pat, int left, int right, unsigned n, int bits) in bitfill_unaligned() argument
101 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); in bitfill_unaligned()
103 if (dst_idx+n <= bits) { in bitfill_unaligned()
115 n -= bits - dst_idx; in bitfill_unaligned()
119 n /= bits; in bitfill_unaligned()
[all …]
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| /drivers/staging/comedi/drivers/ |
| D | c6xdigio.c | 71 unsigned int *bits, in c6xdigio_get_encoder_bits() argument
81 *bits = val; in c6xdigio_get_encoder_bits()
90 unsigned int bits; in c6xdigio_pwm_write() local
97 bits = (val >> 0) & 0x03; in c6xdigio_pwm_write()
98 c6xdigio_write_data(dev, cmd | bits | (0 << 2), 0x00); in c6xdigio_pwm_write()
99 bits = (val >> 2) & 0x03; in c6xdigio_pwm_write()
100 c6xdigio_write_data(dev, cmd | bits | (1 << 2), 0x80); in c6xdigio_pwm_write()
101 bits = (val >> 4) & 0x03; in c6xdigio_pwm_write()
102 c6xdigio_write_data(dev, cmd | bits | (0 << 2), 0x00); in c6xdigio_pwm_write()
103 bits = (val >> 6) & 0x03; in c6xdigio_pwm_write()
[all …]
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| /drivers/block/drbd/ |
| D | drbd_vli.h | 207 static inline void bitstream_cursor_advance(struct bitstream_cursor *cur, unsigned int bits) in bitstream_cursor_advance() argument
209 bits += cur->bit; in bitstream_cursor_advance()
210 cur->b = cur->b + (bits >> 3); in bitstream_cursor_advance()
211 cur->bit = bits & 7; in bitstream_cursor_advance()
248 static inline int bitstream_put_bits(struct bitstream *bs, u64 val, const unsigned int bits) in bitstream_put_bits() argument
253 if (bits == 0) in bitstream_put_bits()
256 if ((bs->cur.b + ((bs->cur.bit + bits -1) >> 3)) - bs->buf >= bs->buf_len) in bitstream_put_bits()
260 if (bits < 64) in bitstream_put_bits()
261 val &= ~0ULL >> (64 - bits); in bitstream_put_bits()
265 for (tmp = 8 - bs->cur.bit; tmp < bits; tmp += 8) in bitstream_put_bits()
[all …]
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| /drivers/iio/adc/ |
| D | max1363.c | 141 u8 bits; member
388 if (st->chip_info->bits != 8) { in max1363_read_single_chan()
396 ((1 << st->chip_info->bits) - 1); in max1363_read_single_chan()
430 *val2 = st->chip_info->bits; in max1363_read_raw()
460 #define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \ argument
471 .realbits = bits, \
472 .storagebits = (bits > 8) ? 16 : 8, \
481 #define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \ argument
494 .realbits = bits, \
495 .storagebits = (bits > 8) ? 16 : 8, \
[all …]
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| D | ti-ads7950.c | 53 #define TI_ADS7950_EXTRACT(val, dec, bits) \ argument
54 (((val) >> (dec)) & ((1 << (bits)) - 1))
136 #define TI_ADS7950_V_CHAN(index, bits) \ argument
148 .realbits = bits, \
150 .shift = 12 - (bits), \
155 #define DECLARE_TI_ADS7950_4_CHANNELS(name, bits) \ argument
157 TI_ADS7950_V_CHAN(0, bits), \
158 TI_ADS7950_V_CHAN(1, bits), \
159 TI_ADS7950_V_CHAN(2, bits), \
160 TI_ADS7950_V_CHAN(3, bits), \
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| D | ad7476.c | 141 #define _AD7476_CHAN(bits, _shift, _info_mask_sep) \ argument
149 .realbits = (bits), \
156 #define ADC081S_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \ argument
158 #define AD7476_CHAN(bits) _AD7476_CHAN((bits), 13 - (bits), \ argument
160 #define AD7940_CHAN(bits) _AD7476_CHAN((bits), 15 - (bits), \ argument
162 #define AD7091R_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), 0) argument
163 #define ADS786X_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \ argument
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| /drivers/iio/dac/ |
| D | ad5686.c | 191 #define AD5868_CHANNEL(chan, addr, bits, _shift) { \ argument
201 .realbits = (bits), \
208 #define DECLARE_AD5693_CHANNELS(name, bits, _shift) \ argument
210 AD5868_CHANNEL(0, 0, bits, _shift), \
213 #define DECLARE_AD5686_CHANNELS(name, bits, _shift) \ argument
215 AD5868_CHANNEL(0, 1, bits, _shift), \
216 AD5868_CHANNEL(1, 2, bits, _shift), \
217 AD5868_CHANNEL(2, 4, bits, _shift), \
218 AD5868_CHANNEL(3, 8, bits, _shift), \
221 #define DECLARE_AD5676_CHANNELS(name, bits, _shift) \ argument
[all …]
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc_dp_types.h | 141 } bits; member
151 } bits; member
161 } bits; member
169 } bits; member
179 } bits; member
193 } bits; member
207 } bits; member
216 } bits; member
227 } bits; member
236 } bits; member
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| /drivers/clk/at91/ |
| D | sckc.c | 32 const struct clk_slow_bits *bits; member
41 const struct clk_slow_bits *bits; member
51 const struct clk_slow_bits *bits; member
62 const struct clk_slow_bits *bits; member
74 if (tmp & (osc->bits->cr_osc32byp | osc->bits->cr_osc32en)) in clk_slow_osc_prepare()
77 writel(tmp | osc->bits->cr_osc32en, sckcr); in clk_slow_osc_prepare()
93 if (tmp & osc->bits->cr_osc32byp) in clk_slow_osc_unprepare()
96 writel(tmp & ~osc->bits->cr_osc32en, sckcr); in clk_slow_osc_unprepare()
105 if (tmp & osc->bits->cr_osc32byp) in clk_slow_osc_is_prepared()
108 return !!(tmp & osc->bits->cr_osc32en); in clk_slow_osc_is_prepared()
[all …]
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| /drivers/net/ethernet/neterion/vxge/ |
| D | vxge-reg.h | 31 #define vxge_bVALn(bits, loc, n) \ argument
32 ((((u64)bits) >> (64-(loc+n))) & ((0x1ULL << n) - 1))
34 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(bits) \ argument
35 vxge_bVALn(bits, 0, 16)
36 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(bits) \ argument
37 vxge_bVALn(bits, 48, 8)
38 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(bits) \ argument
39 vxge_bVALn(bits, 56, 8)
41 #define VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(bits) \ argument
42 vxge_bVALn(bits, 3, 5)
[all …]
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| /drivers/net/ethernet/ti/ |
| D | cpsw_ale.c | 21 #define BITMASK(bits) (BIT(bits) - 1) argument
61 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) in cpsw_ale_get_field() argument
68 return (ale_entry[idx] >> start) & BITMASK(bits); in cpsw_ale_get_field()
71 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits, in cpsw_ale_set_field() argument
76 value &= BITMASK(bits); in cpsw_ale_set_field()
80 ale_entry[idx] &= ~(BITMASK(bits) << start); in cpsw_ale_set_field()
84 #define DEFINE_ALE_FIELD(name, start, bits) \ argument
87 return cpsw_ale_get_field(ale_entry, start, bits); \
91 cpsw_ale_set_field(ale_entry, start, bits, value); \
95 static inline int cpsw_ale_get_##name(u32 *ale_entry, u32 bits) \
[all …]
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| /drivers/spi/ |
| D | spi-bitbang-txrx.h | 49 u32 word, u8 bits) in bitbang_txrx_be_cpha0() argument
53 u32 oldbit = (!(word & (1<<(bits-1)))) << 31; in bitbang_txrx_be_cpha0()
55 for (word <<= (32 - bits); likely(bits); bits--) { in bitbang_txrx_be_cpha0()
81 u32 word, u8 bits) in bitbang_txrx_be_cpha1() argument
85 u32 oldbit = (!(word & (1<<(bits-1)))) << 31; in bitbang_txrx_be_cpha1()
87 for (word <<= (32 - bits); likely(bits); bits--) { in bitbang_txrx_be_cpha1()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_dmcu.c | 229 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; in dce_dmcu_setup_psr()
230 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; in dce_dmcu_setup_psr()
231 masterCmdData1.bits.rfb_update_auto_en = in dce_dmcu_setup_psr()
233 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; in dce_dmcu_setup_psr()
234 masterCmdData1.bits.dcp_sel = psr_context->controllerId; in dce_dmcu_setup_psr()
235 masterCmdData1.bits.phy_type = psr_context->phyType; in dce_dmcu_setup_psr()
236 masterCmdData1.bits.frame_cap_ind = in dce_dmcu_setup_psr()
238 masterCmdData1.bits.aux_chan = psr_context->channel; in dce_dmcu_setup_psr()
239 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; in dce_dmcu_setup_psr()
244 masterCmdData2.bits.dig_fe = psr_context->engineId; in dce_dmcu_setup_psr()
[all …]
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| /drivers/gpu/drm/tegra/ |
| D | hda.c | 14 unsigned int mul, div, bits, channels; in tegra_hda_parse_format() local
33 fmt->bits = 8; in tegra_hda_parse_format()
37 fmt->bits = 16; in tegra_hda_parse_format()
41 fmt->bits = 20; in tegra_hda_parse_format()
45 fmt->bits = 24; in tegra_hda_parse_format()
49 fmt->bits = 32; in tegra_hda_parse_format()
53 bits = (format & AC_FMT_BITS_MASK) >> AC_FMT_BITS_SHIFT; in tegra_hda_parse_format()
54 WARN(1, "invalid number of bits: %#x\n", bits); in tegra_hda_parse_format()
55 fmt->bits = 8; in tegra_hda_parse_format()
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| /drivers/net/ethernet/brocade/bna/ |
| D | bna_hw_defs.h | 88 (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0 | \
90 (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0 | \
92 (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK); \
93 (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK); \
94 (_bna)->bits.halt_status_bits = __HFN_INT_LL_HALT; \
95 (_bna)->bits.halt_mask_bits = __HFN_INT_LL_HALT; \
108 (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0_CT2 | \
110 (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0_CT2 | \
112 (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK_CT2); \
113 (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK_CT2); \
[all …]
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| /drivers/gpu/drm/i915/ |
| D | i915_irq.h | 48 u32 bits);
53 ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits) in ilk_enable_display_irq() argument
55 ilk_update_display_irq(dev_priv, bits, bits); in ilk_enable_display_irq()
58 ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits) in ilk_disable_display_irq() argument
60 ilk_update_display_irq(dev_priv, bits, 0); in ilk_disable_display_irq()
67 enum pipe pipe, u32 bits) in bdw_enable_pipe_irq() argument
69 bdw_update_pipe_irq(dev_priv, pipe, bits, bits); in bdw_enable_pipe_irq()
72 enum pipe pipe, u32 bits) in bdw_disable_pipe_irq() argument
74 bdw_update_pipe_irq(dev_priv, pipe, bits, 0); in bdw_disable_pipe_irq()
80 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits) in ibx_enable_display_interrupt() argument
[all …]
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| /drivers/media/rc/ |
| D | ir-imon-decoder.c | 43 if (imon->bits == 0x299115b7) in ir_imon_decode_scancode()
46 if ((imon->bits & 0xfc0000ff) == 0x680000b7) { in ir_imon_decode_scancode()
50 buf = imon->bits >> 16; in ir_imon_decode_scancode()
53 if (imon->bits & 0x02000000) in ir_imon_decode_scancode()
55 buf = imon->bits >> 8; in ir_imon_decode_scancode()
58 if (imon->bits & 0x01000000) in ir_imon_decode_scancode()
63 imon->bits = rel_y > 0 ? in ir_imon_decode_scancode()
67 imon->bits = rel_x > 0 ? in ir_imon_decode_scancode()
77 (imon->bits & 0x00010000) != 0); in ir_imon_decode_scancode()
79 (imon->bits & 0x00040000) != 0); in ir_imon_decode_scancode()
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| /drivers/gpu/drm/zte/ |
| D | zx_vou.c | 128 const struct zx_crtc_bits *bits; member
294 const struct zx_crtc_bits *bits = zcrtc->bits; in zx_vou_config_dividers() local
307 shift = bits->div_vga_shift; in zx_vou_config_dividers()
311 shift = bits->div_pic_shift; in zx_vou_config_dividers()
315 shift = bits->div_tvenc_shift; in zx_vou_config_dividers()
319 shift = bits->div_hdmi_pnx_shift; in zx_vou_config_dividers()
323 shift = bits->div_hdmi_shift; in zx_vou_config_dividers()
327 shift = bits->div_inf_shift; in zx_vou_config_dividers()
331 shift = bits->div_layer_shift; in zx_vou_config_dividers()
360 const struct zx_crtc_bits *bits = zcrtc->bits; in zx_crtc_atomic_enable() local
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| /drivers/soc/imx/ |
| D | gpcv2.c | 117 } bits; member
143 domain->bits.map, domain->bits.map); in imx_gpc_pu_pgc_sw_pxx_req()
161 if (domain->bits.hsk) in imx_gpc_pu_pgc_sw_pxx_req()
163 domain->bits.hsk, on ? domain->bits.hsk : 0); in imx_gpc_pu_pgc_sw_pxx_req()
166 domain->bits.pxx, domain->bits.pxx); in imx_gpc_pu_pgc_sw_pxx_req()
173 !(pxx_req & domain->bits.pxx), in imx_gpc_pu_pgc_sw_pxx_req()
207 domain->bits.map, 0); in imx_gpc_pu_pgc_sw_pxx_req()
226 .bits = {
238 .bits = {
250 .bits = {
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| /drivers/s390/cio/ |
| D | airq.c | 120 static inline unsigned long iv_size(unsigned long bits) in iv_size() argument
122 return BITS_TO_LONGS(bits) * sizeof(unsigned long); in iv_size()
132 struct airq_iv *airq_iv_create(unsigned long bits, unsigned long flags) in airq_iv_create() argument
140 iv->bits = bits; in airq_iv_create()
142 size = iv_size(bits); in airq_iv_create()
145 if ((cache_line_size() * BITS_PER_BYTE) < bits in airq_iv_create()
165 iv->end = bits; in airq_iv_create()
172 size = bits * sizeof(unsigned long); in airq_iv_create()
178 size = bits * sizeof(unsigned int); in airq_iv_create()
212 cio_dma_free(iv->vector, iv_size(iv->bits)); in airq_iv_release()
[all …]
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_dp.c | 70 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL) in get_training_aux_rd_interval()
71 default_wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000; in get_training_aux_rd_interval()
110 if (features->flags.bits.IS_TPS3_CAPABLE) in get_supported_tp()
113 if (features->flags.bits.IS_TPS4_CAPABLE) in get_supported_tp()
116 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED && in get_supported_tp()
120 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED && in get_supported_tp()
140 lane_count_set.bits.LANE_COUNT_SET = in dpcd_set_link_settings()
143 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing; in dpcd_set_link_settings()
144 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0; in dpcd_set_link_settings()
149 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = in dpcd_set_link_settings()
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