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Searched refs:cc_ioread (Results 1 – 5 of 5) sorted by relevance

/drivers/crypto/ccree/
Dcc_driver.c110 idr.regs[i] = cc_ioread(drvdata, idr_offsets[i]); in cc_read_idr()
141 irr = cc_ioread(drvdata, CC_REG(HOST_IRR)); in cc_isr()
147 imr = cc_ioread(drvdata, CC_REG(HOST_IMR)); in cc_isr()
178 axi_err = cc_ioread(drvdata, CC_REG(AXIM_MON_ERR)); in cc_isr()
207 val = cc_ioread(drvdata, CC_REG(NVM_IS_IDLE)); in cc_wait_for_reset_completion()
227 val = cc_ioread(drvdata, CC_REG(AXIM_CFG)); in init_cc_regs()
230 cc_ioread(drvdata, CC_REG(AXIM_CFG))); in init_cc_regs()
234 val = cc_ioread(drvdata, CC_REG(HOST_IRR)); in init_cc_regs()
248 val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS)); in init_cc_regs()
254 val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS)); in init_cc_regs()
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Dcc_request_mgr.c147 req_mgr_h->hw_queue_size = cc_ioread(drvdata, in cc_req_mgr_init()
249 cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT)); in cc_queues_status()
543 cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT)); in send_request_init()
626 cc_ioread(drvdata, drvdata->axim_mon_offset)); in cc_axi_comp_count()
655 drvdata->irq |= cc_ioread(drvdata, CC_REG(HOST_IRR)); in comp_handler()
675 cc_ioread(drvdata, CC_REG(HOST_IMR)) & ~drvdata->comp_mask); in comp_handler()
Dcc_sram_mgr.c40 start = (dma_addr_t)cc_ioread(drvdata, in cc_sram_mgr_init()
Dcc_fips.c26 reg = cc_ioread(drvdata, CC_REG(GPR_HOST)); in cc_get_tee_fips_status()
Dcc_driver.h226 static inline u32 cc_ioread(struct cc_drvdata *drvdata, u32 reg) in cc_ioread() function