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Searched refs:chip_types (Results 1 – 25 of 41) sorted by relevance

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/drivers/irqchip/
Dirq-sunxi-nmi.c113 struct irq_chip_type *ct = gc->chip_types; in sunxi_sc_nmi_set_type()
198 gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; in sunxi_sc_nmi_irq_init()
199 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in sunxi_sc_nmi_irq_init()
200 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in sunxi_sc_nmi_irq_init()
201 gc->chip_types[0].chip.irq_eoi = irq_gc_ack_set_bit; in sunxi_sc_nmi_irq_init()
202 gc->chip_types[0].chip.irq_set_type = sunxi_sc_nmi_set_type; in sunxi_sc_nmi_irq_init()
203 gc->chip_types[0].chip.flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED; in sunxi_sc_nmi_irq_init()
204 gc->chip_types[0].regs.ack = reg_offs->pend; in sunxi_sc_nmi_irq_init()
205 gc->chip_types[0].regs.mask = reg_offs->enable; in sunxi_sc_nmi_irq_init()
206 gc->chip_types[0].regs.type = reg_offs->ctrl; in sunxi_sc_nmi_irq_init()
[all …]
Dirq-tb10x.c146 gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; in of_tb10x_init_irq()
147 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in of_tb10x_init_irq()
148 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in of_tb10x_init_irq()
149 gc->chip_types[0].chip.irq_set_type = tb10x_irq_set_type; in of_tb10x_init_irq()
150 gc->chip_types[0].regs.mask = AB_IRQCTL_INT_ENABLE; in of_tb10x_init_irq()
152 gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; in of_tb10x_init_irq()
153 gc->chip_types[1].chip.name = gc->chip_types[0].chip.name; in of_tb10x_init_irq()
154 gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit; in of_tb10x_init_irq()
155 gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit; in of_tb10x_init_irq()
156 gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit; in of_tb10x_init_irq()
[all …]
Dirq-imgpdc.c409 gc->chip_types[0].regs.mask = PDC_IRQ_ROUTE; in pdc_intc_probe()
410 gc->chip_types[0].chip.irq_mask = perip_irq_mask; in pdc_intc_probe()
411 gc->chip_types[0].chip.irq_unmask = perip_irq_unmask; in pdc_intc_probe()
412 gc->chip_types[0].chip.irq_set_wake = pdc_irq_set_wake; in pdc_intc_probe()
421 gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH; in pdc_intc_probe()
422 gc->chip_types[0].handler = handle_edge_irq; in pdc_intc_probe()
423 gc->chip_types[0].regs.ack = PDC_IRQ_CLEAR; in pdc_intc_probe()
424 gc->chip_types[0].regs.mask = PDC_IRQ_ENABLE; in pdc_intc_probe()
425 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; in pdc_intc_probe()
426 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in pdc_intc_probe()
[all …]
Dirq-pic32-evic.c272 gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; in pic32_of_init()
273 gc->chip_types[0].handler = handle_fasteoi_irq; in pic32_of_init()
274 gc->chip_types[0].regs.ack = ifsclr; in pic32_of_init()
275 gc->chip_types[0].regs.mask = iec; in pic32_of_init()
276 gc->chip_types[0].chip.name = "evic-level"; in pic32_of_init()
277 gc->chip_types[0].chip.irq_eoi = irq_gc_ack_set_bit; in pic32_of_init()
278 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in pic32_of_init()
279 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in pic32_of_init()
280 gc->chip_types[0].chip.flags = IRQCHIP_SKIP_SET_WAKE; in pic32_of_init()
283 gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; in pic32_of_init()
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Dirq-zevio.c106 gc->chip_types[0].chip.irq_ack = zevio_irq_ack; in zevio_of_init()
107 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; in zevio_of_init()
108 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; in zevio_of_init()
109 gc->chip_types[0].regs.mask = IO_IRQ_BASE + IO_ENABLE; in zevio_of_init()
110 gc->chip_types[0].regs.enable = IO_IRQ_BASE + IO_ENABLE; in zevio_of_init()
111 gc->chip_types[0].regs.disable = IO_IRQ_BASE + IO_DISABLE; in zevio_of_init()
112 gc->chip_types[0].regs.ack = IO_IRQ_BASE + IO_RESET; in zevio_of_init()
Dirq-atmel-aic.c258 gc->chip_types[0].regs.eoi = AT91_AIC_EOICR; in aic_of_init()
259 gc->chip_types[0].regs.enable = AT91_AIC_IECR; in aic_of_init()
260 gc->chip_types[0].regs.disable = AT91_AIC_IDCR; in aic_of_init()
261 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; in aic_of_init()
262 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; in aic_of_init()
263 gc->chip_types[0].chip.irq_retrigger = aic_retrigger; in aic_of_init()
264 gc->chip_types[0].chip.irq_set_type = aic_set_type; in aic_of_init()
265 gc->chip_types[0].chip.irq_suspend = aic_suspend; in aic_of_init()
266 gc->chip_types[0].chip.irq_resume = aic_resume; in aic_of_init()
267 gc->chip_types[0].chip.irq_pm_shutdown = aic_pm_shutdown; in aic_of_init()
Dirq-orion.c90 gc->chip_types[0].regs.mask = ORION_IRQ_MASK; in orion_irq_init()
91 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in orion_irq_init()
92 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in orion_irq_init()
189 gc->chip_types[0].regs.ack = ORION_BRIDGE_IRQ_CAUSE; in orion_bridge_irq_init()
190 gc->chip_types[0].regs.mask = ORION_BRIDGE_IRQ_MASK; in orion_bridge_irq_init()
191 gc->chip_types[0].chip.irq_startup = orion_bridge_irq_startup; in orion_bridge_irq_init()
192 gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit; in orion_bridge_irq_init()
193 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in orion_bridge_irq_init()
194 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in orion_bridge_irq_init()
Dirq-al-fic.c59 gc->chip_types->handler = handler; in al_fic_set_trigger()
167 gc->chip_types->regs.mask = AL_FIC_MASK; in al_fic_register()
168 gc->chip_types->regs.ack = AL_FIC_CAUSE; in al_fic_register()
169 gc->chip_types->chip.irq_mask = irq_gc_mask_set_bit; in al_fic_register()
170 gc->chip_types->chip.irq_unmask = irq_gc_mask_clr_bit; in al_fic_register()
171 gc->chip_types->chip.irq_ack = irq_gc_ack_clr_bit; in al_fic_register()
172 gc->chip_types->chip.irq_set_type = al_fic_irq_set_type; in al_fic_register()
173 gc->chip_types->chip.irq_retrigger = al_fic_irq_retrigger; in al_fic_register()
174 gc->chip_types->chip.flags = IRQCHIP_SKIP_SET_WAKE; in al_fic_register()
Dirq-digicolor.c64 gc->chip_types[0].regs.ack = ack_reg; in digicolor_set_gc()
65 gc->chip_types[0].regs.mask = en_reg; in digicolor_set_gc()
66 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; in digicolor_set_gc()
67 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in digicolor_set_gc()
68 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in digicolor_set_gc()
Dirq-renesas-irqc.c188 p->gc->chip_types[0].regs.enable = IRQC_EN_SET; in irqc_probe()
189 p->gc->chip_types[0].regs.disable = IRQC_EN_STS; in irqc_probe()
190 p->gc->chip_types[0].chip.parent_device = dev; in irqc_probe()
191 p->gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; in irqc_probe()
192 p->gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; in irqc_probe()
193 p->gc->chip_types[0].chip.irq_set_type = irqc_irq_set_type; in irqc_probe()
194 p->gc->chip_types[0].chip.irq_set_wake = irqc_irq_set_wake; in irqc_probe()
195 p->gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND; in irqc_probe()
Dirq-mscc-ocelot.c95 gc->chip_types[0].regs.ack = ICPU_CFG_INTR_INTR_STICKY; in ocelot_irq_init()
96 gc->chip_types[0].regs.mask = ICPU_CFG_INTR_INTR_ENA_CLR; in ocelot_irq_init()
97 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; in ocelot_irq_init()
98 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; in ocelot_irq_init()
99 gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask; in ocelot_irq_init()
Dirq-nvic.c125 gc->chip_types[0].regs.enable = NVIC_ISER; in nvic_of_init()
126 gc->chip_types[0].regs.disable = NVIC_ICER; in nvic_of_init()
127 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; in nvic_of_init()
128 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; in nvic_of_init()
132 gc->chip_types[0].chip.irq_eoi = irq_gc_noop; in nvic_of_init()
Dirq-dw-apb-ictl.c142 gc->chip_types[0].regs.mask = APB_INT_MASK_L; in dw_apb_ictl_init()
143 gc->chip_types[0].regs.enable = APB_INT_ENABLE_L; in dw_apb_ictl_init()
144 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; in dw_apb_ictl_init()
145 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; in dw_apb_ictl_init()
146 gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume; in dw_apb_ictl_init()
Dirq-atmel-aic5.c345 gc->chip_types[0].regs.eoi = AT91_AIC5_EOICR; in aic5_of_init()
346 gc->chip_types[0].chip.irq_mask = aic5_mask; in aic5_of_init()
347 gc->chip_types[0].chip.irq_unmask = aic5_unmask; in aic5_of_init()
348 gc->chip_types[0].chip.irq_retrigger = aic5_retrigger; in aic5_of_init()
349 gc->chip_types[0].chip.irq_set_type = aic5_set_type; in aic5_of_init()
350 gc->chip_types[0].chip.irq_suspend = aic5_suspend; in aic5_of_init()
351 gc->chip_types[0].chip.irq_resume = aic5_resume; in aic5_of_init()
352 gc->chip_types[0].chip.irq_pm_shutdown = aic5_pm_shutdown; in aic5_of_init()
Dirq-atmel-aic-common.c253 gc->chip_types[0].type = IRQ_TYPE_SENSE_MASK; in aic_common_of_init()
254 gc->chip_types[0].chip.irq_eoi = irq_gc_eoi; in aic_common_of_init()
255 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; in aic_common_of_init()
256 gc->chip_types[0].chip.irq_shutdown = aic_common_shutdown; in aic_common_of_init()
Dirq-csky-apb-intc.c67 gc->chip_types[0].regs.mask = mask_reg; in ck_set_gc()
68 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in ck_set_gc()
69 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in ck_set_gc()
72 gc->chip_types[0].chip.irq_unmask = irq_ck_mask_set_bit; in ck_set_gc()
Dirq-stm32-exti.c754 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; in stm32_exti_init()
755 gc->chip_types->chip.irq_ack = stm32_irq_ack; in stm32_exti_init()
756 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; in stm32_exti_init()
757 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; in stm32_exti_init()
758 gc->chip_types->chip.irq_set_type = stm32_irq_set_type; in stm32_exti_init()
759 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake; in stm32_exti_init()
764 gc->chip_types->regs.mask = stm32_bank->imr_ofst; in stm32_exti_init()
Dirq-ingenic.c55 struct irq_chip_regs *regs = &gc->chip_types->regs; in intc_irq_set_mask()
131 ct = gc->chip_types; in ingenic_intc_of_init()
Dirq-bcm7120-l2.c89 struct irq_chip_type *ct = gc->chip_types; in bcm7120_l2_intc_suspend()
100 struct irq_chip_type *ct = gc->chip_types; in bcm7120_l2_intc_resume()
286 ct = gc->chip_types; in bcm7120_l2_intc_probe()
Dirq-tango.c92 struct irq_chip_regs *regs = &gc->chip_types[0].regs; in tangox_irq_set_type()
129 struct irq_chip_type *ct = gc->chip_types; in tangox_irq_init_chip()
Dirq-omap-intc.c206 ct = gc->chip_types; in omap_alloc_gc_of()
231 ct = gc->chip_types; in omap_alloc_gc_legacy()
Dirq-goldfish-pic.c96 ct = gc->chip_types; in goldfish_pic_of_init()
/drivers/gpio/
Dgpio-tb10x.c202 gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH; in tb10x_gpio_probe()
203 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; in tb10x_gpio_probe()
204 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in tb10x_gpio_probe()
205 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in tb10x_gpio_probe()
206 gc->chip_types[0].chip.irq_set_type = tb10x_gpio_irq_set_type; in tb10x_gpio_probe()
207 gc->chip_types[0].regs.ack = OFFSET_TO_REG_CHANGE; in tb10x_gpio_probe()
208 gc->chip_types[0].regs.mask = OFFSET_TO_REG_INT_EN; in tb10x_gpio_probe()
Dgpio-dwapb.c422 ct = &irq_gc->chip_types[i]; in dwapb_configure_irqs()
439 irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; in dwapb_configure_irqs()
440 irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; in dwapb_configure_irqs()
441 irq_gc->chip_types[1].handler = handle_edge_irq; in dwapb_configure_irqs()
/drivers/soc/dove/
Dpmu.c296 gc->chip_types[0].regs.mask = PMC_IRQ_MASK; in dove_init_pmu_irq()
297 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in dove_init_pmu_irq()
298 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in dove_init_pmu_irq()

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