| /drivers/clk/mxs/ |
| D | clk-pll.c | 23 struct clk_pll { struct
30 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) argument
34 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare()
45 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_unprepare()
52 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable()
61 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_disable()
69 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate()
85 struct clk_pll *pll; in mxs_clk_pll()
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| /drivers/clk/qcom/ |
| D | clk-pll.c | 26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable()
67 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_disable()
82 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate()
128 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_determine_rate()
143 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_set_rate()
179 static int wait_for_pll(struct clk_pll *pll) in wait_for_pll()
203 struct clk_pll *p = to_clk_pll(clk_hw_get_parent(hw)); in clk_pll_vote_enable()
218 static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap, in clk_pll_configure()
245 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap, in clk_pll_configure_sr()
254 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, in clk_pll_configure_sr_hpm_lp()
[all …]
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| D | clk-pll.h | 39 struct clk_pll { struct
59 #define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr) argument
76 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
78 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
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| D | a53-pll.c | 42 struct clk_pll *pll; in qcom_a53pll_probe()
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| D | gcc-mdm9615.c | 40 static struct clk_pll pll0 = {
78 static struct clk_pll pll8 = {
105 static struct clk_pll pll14 = {
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| D | gcc-ipq806x.c | 28 static struct clk_pll pll0 = {
55 static struct clk_pll pll3 = {
82 static struct clk_pll pll8 = {
187 static struct clk_pll pll14 = {
228 static struct clk_pll pll18 = {
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| D | lcc-ipq806x.c | 26 static struct clk_pll pll4 = {
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| D | mmcc-msm8974.c | 179 static struct clk_pll mmpll0 = {
206 static struct clk_pll mmpll1 = {
233 static struct clk_pll mmpll2 = {
248 static struct clk_pll mmpll3 = {
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| D | mmcc-apq8084.c | 214 static struct clk_pll mmpll0 = {
241 static struct clk_pll mmpll1 = {
268 static struct clk_pll mmpll2 = {
283 static struct clk_pll mmpll3 = {
299 static struct clk_pll mmpll4 = {
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| D | lcc-mdm9615.c | 28 static struct clk_pll pll4 = {
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| D | lcc-msm8960.c | 26 static struct clk_pll pll4 = {
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| D | gcc-msm8916.c | 259 static struct clk_pll gpll0 = {
286 static struct clk_pll gpll1 = {
313 static struct clk_pll gpll2 = {
340 static struct clk_pll bimc_pll = {
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| D | gcc-msm8974.c | 57 static struct clk_pll gpll0 = {
120 static struct clk_pll gpll1 = {
147 static struct clk_pll gpll4 = {
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| /drivers/clk/at91/ |
| D | clk-pll.c | 32 #define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
34 struct clk_pll { struct
56 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() argument
99 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_is_prepared()
106 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_unprepare()
115 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate()
123 static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate, in clk_pll_get_best_div_mul()
236 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_round_rate()
245 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_set_rate()
278 struct clk_pll *pll; in at91_clk_register_pll()
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| /drivers/clk/ |
| D | clk-nomadik.c | 142 struct clk_pll { struct
161 #define to_pll(_hw) container_of(_hw, struct clk_pll, hw) argument
166 struct clk_pll *pll = to_pll(hw); in pll_clk_enable()
186 struct clk_pll *pll = to_pll(hw); in pll_clk_disable()
205 struct clk_pll *pll = to_pll(hw); in pll_clk_is_enabled()
221 struct clk_pll *pll = to_pll(hw); in pll_clk_recalc_rate()
261 struct clk_pll *pll; in pll_clk_register()
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| D | clk-vt8500.c | 41 struct clk_pll { struct
308 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
549 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_set_rate()
600 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_round_rate()
639 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_recalc_rate()
677 struct clk_pll *pll_clk; in vtwm_pll_clk_init()
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| D | clk-versaclock5.c | 158 struct vc5_hw_data clk_pll; member
803 vc5->clk_pll.num = 0; in vc5_probe()
804 vc5->clk_pll.vc5 = vc5; in vc5_probe()
805 vc5->clk_pll.hw.init = &init; in vc5_probe()
806 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw); in vc5_probe()
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| /drivers/clk/spear/ |
| D | clk-vco-pll.c | 66 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
87 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_round_rate_index()
127 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate()
147 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_set_rate()
283 struct clk_pll *pll; in clk_register_vco_pll()
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| D | clk.h | 102 struct clk_pll { struct
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| /drivers/clk/keystone/ |
| D | pll.c | 68 struct clk_pll { struct
73 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) argument
78 struct clk_pll *pll = to_clk_pll(hw); in clk_pllclk_recalc()
126 struct clk_pll *pll; in clk_register_pll()
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| /drivers/clk/sirf/ |
| D | clk-common.c | 33 struct clk_pll { struct
38 #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw) argument
77 struct clk_pll *clk = to_pllclk(hw); in pll_clk_recalc_rate()
129 struct clk_pll *clk = to_pllclk(hw); in pll_clk_set_rate()
217 static struct clk_pll clk_pll1 = {
224 static struct clk_pll clk_pll2 = {
231 static struct clk_pll clk_pll3 = {
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| D | clk-atlas7.c | 213 struct clk_pll { struct
217 #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw) argument
356 struct clk_pll *clk = to_pllclk(hw); in pll_clk_recalc_rate()
401 static struct clk_pll clk_cpupll = {
415 static struct clk_pll clk_mempll = {
429 static struct clk_pll clk_sys0pll = {
443 static struct clk_pll clk_sys1pll = {
457 static struct clk_pll clk_sys2pll = {
471 static struct clk_pll clk_sys3pll = {
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| /drivers/gpu/drm/imx/ |
| D | imx-ldb.c | 93 struct clk *clk_pll[2]; /* upstream clock we can adjust */ member
171 clk_get_rate(ldb->clk_pll[chno]), serial_clk); in imx_ldb_set_clock()
172 clk_set_rate(ldb->clk_pll[chno], serial_clk); in imx_ldb_set_clock()
175 clk_get_rate(ldb->clk_pll[chno])); in imx_ldb_set_clock()
416 ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname); in imx_ldb_get_clk()
418 return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]); in imx_ldb_get_clk()
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| /drivers/staging/most/dim2/ |
| D | dim2.c | 94 struct clk *clk_pll; member
933 dev->clk_pll = devm_clk_get(&pdev->dev, "pll8_mlb"); in fsl_mx6_enable()
934 if (IS_ERR_OR_NULL(dev->clk_pll)) { in fsl_mx6_enable()
941 clk_prepare_enable(dev->clk_pll); in fsl_mx6_enable()
952 clk_disable_unprepare(dev->clk_pll); in fsl_mx6_disable()
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| /drivers/clk/ti/ |
| D | fapll.c | 83 struct clk *clk_pll; member
521 synth->clk_pll = pll_clk; in ti_fapll_synth_setup()
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