Searched refs:clks_cfg (Results 1 – 9 of 9) sorted by relevance
2530 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn20_calculate_wm()2531 …pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw… in dcn20_calculate_wm()2534 pipes[pipe_cnt].clks_cfg.dppclk_mhz = in dcn20_calculate_wm()2543 pipes[pipe_cnt].clks_cfg.dppclk_mhz = in dcn20_calculate_wm()2553 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn20_calculate_wm()2554 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn20_calculate_wm()2556 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000) in dcn20_calculate_wm()2557 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn20_calculate_wm()2558 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000) in dcn20_calculate_wm()2559 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn20_calculate_wm()[all …]
68 if (need_recalculate && pipes[0].clks_cfg.dppclk_mhz != 0) in dml_get_voltage_level()370 display_clocks_and_cfg_st *clks = &pipes[j].clks_cfg; in fetch_pipe_params()805 mode_lib->vba.VoltageLevel = mode_lib->vba.cache_pipes[0].clks_cfg.voltage; in ModeSupportAndSystemConfiguration()813 mode_lib->vba.DCFCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dcfclk_mhz; in ModeSupportAndSystemConfiguration()814 mode_lib->vba.SOCCLK = mode_lib->vba.cache_pipes[0].clks_cfg.socclk_mhz; in ModeSupportAndSystemConfiguration()815 if (mode_lib->vba.cache_pipes[0].clks_cfg.dispclk_mhz > 0.0) in ModeSupportAndSystemConfiguration()816 mode_lib->vba.DISPCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dispclk_mhz; in ModeSupportAndSystemConfiguration()
349 display_clocks_and_cfg_st clks_cfg; member
1000 double refclk_freq_in_mhz = e2e_pipe_param.clks_cfg.refclk_mhz; in dml1_rq_dlg_get_dlg_params()1001 double dppclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dppclk_mhz; in dml1_rq_dlg_get_dlg_params()1002 double dispclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dispclk_mhz; in dml1_rq_dlg_get_dlg_params()
958 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel()959 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()960 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()995 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn21_calculate_wm()996 …pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context… in dcn21_calculate_wm()999 pipes[pipe_cnt].clks_cfg.dppclk_mhz = in dcn21_calculate_wm()1008 pipes[pipe_cnt].clks_cfg.dppclk_mhz = in dcn21_calculate_wm()
480 input.clks_cfg.dcfclk_mhz = v->dcfclk; in dcn_bw_calc_rq_dlg_ttu()481 input.clks_cfg.dispclk_mhz = v->dispclk; in dcn_bw_calc_rq_dlg_ttu()482 input.clks_cfg.dppclk_mhz = v->dppclk; in dcn_bw_calc_rq_dlg_ttu()483 input.clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn_bw_calc_rq_dlg_ttu()484 input.clks_cfg.socclk_mhz = v->socclk; in dcn_bw_calc_rq_dlg_ttu()485 input.clks_cfg.voltage = v->voltage_level; in dcn_bw_calc_rq_dlg_ttu()
780 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20v2_rq_dlg_get_dlg_params()
780 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20_rq_dlg_get_dlg_params()
827 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()