| /drivers/input/touchscreen/ |
| D | mc13783_ts.c | 71 int cr0, cr1; in mc13783_ts_report_sample() local
83 cr0 = (priv->sample[2] >> 12) & 0xfff; in mc13783_ts_report_sample()
88 x0, x1, x2, y0, y1, y2, cr0, cr1); in mc13783_ts_report_sample()
93 cr0 = (cr0 + cr1) / 2; in mc13783_ts_report_sample()
95 if (!cr0 || !sample_tolerance || in mc13783_ts_report_sample()
99 if (cr0) { in mc13783_ts_report_sample()
104 x1, y1, 0x1000 - cr0); in mc13783_ts_report_sample()
111 cr0 ? 0x1000 - cr0 : cr0); in mc13783_ts_report_sample()
112 input_report_key(idev, BTN_TOUCH, cr0); in mc13783_ts_report_sample()
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| /drivers/cpufreq/ |
| D | powernow-k6.c | 105 unsigned long cr0; in powernow_k6_set_cpu_multiplier() local
114 cr0 = read_cr0(); in powernow_k6_set_cpu_multiplier()
115 write_cr0(cr0 | X86_CR0_CD); in powernow_k6_set_cpu_multiplier()
129 write_cr0(cr0); in powernow_k6_set_cpu_multiplier()
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| /drivers/spi/ |
| D | spi-rockchip.c | 462 u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET in rockchip_spi_config() local
469 cr0 |= rs->rsd << CR0_RSD_OFFSET; in rockchip_spi_config()
470 cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET; in rockchip_spi_config()
472 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET; in rockchip_spi_config()
475 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET; in rockchip_spi_config()
477 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET; in rockchip_spi_config()
479 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET; in rockchip_spi_config()
483 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET; in rockchip_spi_config()
487 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET; in rockchip_spi_config()
491 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET; in rockchip_spi_config()
[all …]
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| D | spi-txx9.c | 210 u32 cr0; in txx9spi_work_one() local
217 cr0 = txx9spi_rd(c, TXx9_SPCR0); in txx9spi_work_one()
218 cr0 &= ~TXx9_SPCR0_RXIFL_MASK; in txx9spi_work_one()
219 cr0 |= (count - 1) << 12; in txx9spi_work_one()
221 cr0 |= TXx9_SPCR0_RBSIE; in txx9spi_work_one()
222 txx9spi_wr(c, cr0, TXx9_SPCR0); in txx9spi_work_one()
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| D | spi-ep93xx.c | 153 u16 cr0; in ep93xx_spi_chip_setup() local
161 cr0 = div_scr << SSPCR0_SCR_SHIFT; in ep93xx_spi_chip_setup()
162 cr0 |= (spi->mode & (SPI_CPHA | SPI_CPOL)) << SSPCR0_MODE_SHIFT; in ep93xx_spi_chip_setup()
163 cr0 |= dss; in ep93xx_spi_chip_setup()
167 dev_dbg(&master->dev, "setup: cr0 %#x\n", cr0); in ep93xx_spi_chip_setup()
170 writel(cr0, espi->mmio + SSPCR0); in ep93xx_spi_chip_setup()
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| D | spi-dw.c | 288 u32 cr0; in dw_spi_transfer_one() local
317 cr0 = (transfer->bits_per_word - 1) in dw_spi_transfer_one()
336 cr0 &= ~SPI_TMOD_MASK; in dw_spi_transfer_one()
337 cr0 |= (chip->tmode << SPI_TMOD_OFFSET); in dw_spi_transfer_one()
340 dw_writel(dws, DW_SPI_CTRL0, cr0); in dw_spi_transfer_one()
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| D | spi-pl022.c | 418 u32 cr0; member
563 writel(chip->cr0, SSP_CR0(pl022->virtbase)); in restore_state()
565 writew(chip->cr0, SSP_CR0(pl022->virtbase)); in restore_state()
1973 chip->cr0 = 0; in pl022_setup()
2006 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, in pl022_setup()
2008 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, in pl022_setup()
2010 SSP_WRITE_BITS(chip->cr0, chip_info->iface, in pl022_setup()
2015 SSP_WRITE_BITS(chip->cr0, bits - 1, in pl022_setup()
2032 SSP_WRITE_BITS(chip->cr0, bits - 1, in pl022_setup()
2034 SSP_WRITE_BITS(chip->cr0, chip_info->iface, in pl022_setup()
[all …]
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| D | spi-pxa2xx.c | 930 u32 cr0; in pxa2xx_spi_transfer_one() local
1031 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); in pxa2xx_spi_transfer_one()
1035 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)), in pxa2xx_spi_transfer_one()
1040 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)), in pxa2xx_spi_transfer_one()
1059 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) in pxa2xx_spi_transfer_one()
1063 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); in pxa2xx_spi_transfer_one()
1069 pxa2xx_spi_write(drv_data, SSCR0, cr0); in pxa2xx_spi_transfer_one()
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| /drivers/s390/char/ |
| D | sclp_early_core.c | 31 union ctlreg0 cr0, cr0_new; in sclp_early_wait_irq() local
33 __ctl_store(cr0.val, 0, 0); in sclp_early_wait_irq()
34 cr0_new.val = cr0.val & ~CR0_IRQ_SUBCLASS_MASK; in sclp_early_wait_irq()
60 __ctl_load(cr0.val, 0, 0); in sclp_early_wait_irq()
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| D | sclp.c | 537 unsigned long cr0, cr0_sync; in sclp_sync_wait() local
558 __ctl_store(cr0, 0, 0); in sclp_sync_wait()
559 cr0_sync = cr0 & ~CR0_IRQ_SUBCLASS_MASK; in sclp_sync_wait()
573 __ctl_load(cr0, 0, 0); in sclp_sync_wait()
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| /drivers/crypto/ccp/ |
| D | ccp-dev-v3.c | 79 u32 cr0, cmd; in ccp_do_cmd() local
89 cr0 = (cmd_q->id << REQ0_CMD_Q_SHIFT) in ccp_do_cmd()
94 cr0 |= REQ0_STOP_ON_COMPLETE in ccp_do_cmd()
98 cr0 |= REQ0_INT_ON_COMPLETE; in ccp_do_cmd()
111 iowrite32(cr0, ccp->io_regs + CMD_REQ0); in ccp_do_cmd()
115 if (cr0 & REQ0_INT_ON_COMPLETE) { in ccp_do_cmd()
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| /drivers/video/fbdev/ |
| D | sstfb.c | 970 u8 cr0, cc; in sst_set_pll_att_ti() local
978 cr0 = sst_dac_read(DACREG_RMR); /* 5 CR0 */ in sst_set_pll_att_ti()
985 sst_dac_write(DACREG_RMR, (cr0 & 0xf0) in sst_set_pll_att_ti()
1016 cr0 & ~DACREG_CR0_PWDOWN & ~DACREG_CR0_EN_INDEXED); in sst_set_pll_att_ti()
1061 u8 cr0; in sst_set_vidmod_att_ti() local
1069 cr0 = sst_dac_read(DACREG_RMR); in sst_set_vidmod_att_ti()
1079 sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_16BPP); in sst_set_vidmod_att_ti()
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| /drivers/gpu/drm/mcde/ |
| D | mcde_display.c | 554 u32 cr0, cr1; in mcde_configure_fifo() local
559 cr0 = MCDE_CRA0; in mcde_configure_fifo()
564 cr0 = MCDE_CRB0; in mcde_configure_fifo()
581 writel(val, mcde->regs + cr0); in mcde_configure_fifo()
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