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Searched refs:crtc_w (Results 1 – 25 of 57) sorted by relevance

123

/drivers/gpu/drm/armada/
Darmada_trace.h33 int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
35 TP_ARGS(plane, crtc, fb, crtc_x, crtc_y, crtc_w, crtc_h, src_x, src_y, src_w, src_h),
42 __field(unsigned int, crtc_w)
55 __entry->crtc_w = crtc_w;
65 __entry->crtc_w, __entry->crtc_h,
Darmada_overlay.c253 int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h, in armada_overlay_plane_update() argument
262 crtc_x, crtc_y, crtc_w, crtc_h, in armada_overlay_plane_update()
284 plane_state->crtc_w = crtc_w; in armada_overlay_plane_update()
/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4_plane.c49 unsigned int crtc_w, unsigned int crtc_h,
123 state->crtc_w, state->crtc_h, in mdp4_plane_atomic_update()
195 unsigned int crtc_w, unsigned int crtc_h, in mdp4_plane_mode_set() argument
224 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); in mdp4_plane_mode_set()
228 if (src_w > (crtc_w * DOWN_SCALE_MAX)) { in mdp4_plane_mode_set()
238 if (crtc_w > (src_w * UP_SCALE_MAX)) { in mdp4_plane_mode_set()
248 if (src_w != crtc_w) { in mdp4_plane_mode_set()
253 if (crtc_w > src_w) in mdp4_plane_mode_set()
255 else if (crtc_w <= (src_w / 4)) in mdp4_plane_mode_set()
260 src_w, crtc_w); in mdp4_plane_mode_set()
[all …]
/drivers/gpu/drm/nouveau/dispnv04/
Doverlay.c94 uint32_t crtc_w, uint32_t crtc_h) in verify_scaling() argument
96 if (crtc_w < (src_w >> shift) || crtc_h < (src_h >> shift)) { in verify_scaling()
98 src_w, src_h, crtc_w, crtc_h); in verify_scaling()
114 unsigned int crtc_w, unsigned int crtc_h, in nv10_update_plane() argument
139 ret = verify_scaling(fb, shift, 0, 0, src_w, src_h, crtc_w, crtc_h); in nv10_update_plane()
156 nvif_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w); in nv10_update_plane()
159 nvif_wr32(dev, NV_PVIDEO_SIZE_OUT(flip), crtc_h << 16 | crtc_w); in nv10_update_plane()
363 unsigned int crtc_w, unsigned int crtc_h, in nv04_update_plane() argument
383 ret = verify_scaling(fb, 0, src_x, src_y, src_w, src_h, crtc_w, crtc_h); in nv04_update_plane()
405 nvif_wr32(dev, NV_PVIDEO_WINDOW_SIZE, crtc_h << 16 | crtc_w); in nv04_update_plane()
[all …]
/drivers/gpu/drm/
Ddrm_plane.c600 uint32_t crtc_w, uint32_t crtc_h, in __setplane_check() argument
626 if (crtc_w > INT_MAX || in __setplane_check()
627 crtc_x > INT_MAX - (int32_t) crtc_w || in __setplane_check()
631 crtc_w, crtc_h, crtc_x, crtc_y); in __setplane_check()
677 uint32_t crtc_w, uint32_t crtc_h, in __setplane_internal() argument
701 crtc_x, crtc_y, crtc_w, crtc_h, in __setplane_internal()
708 crtc_x, crtc_y, crtc_w, crtc_h, in __setplane_internal()
730 uint32_t crtc_w, uint32_t crtc_h, in __setplane_atomic() argument
751 crtc_x, crtc_y, crtc_w, crtc_h, in __setplane_atomic()
757 crtc_x, crtc_y, crtc_w, crtc_h, in __setplane_atomic()
[all …]
Ddrm_plane_helper.c123 .crtc_w = drm_rect_width(dst), in drm_plane_helper_check_update()
152 unsigned int crtc_w, unsigned int crtc_h, in drm_primary_helper_update() argument
173 .x2 = crtc_x + crtc_w, in drm_primary_helper_update()
Ddrm_atomic.c586 if (new_plane_state->crtc_w > INT_MAX || in drm_atomic_plane_check()
587 new_plane_state->crtc_x > INT_MAX - (int32_t) new_plane_state->crtc_w || in drm_atomic_plane_check()
592 new_plane_state->crtc_w, new_plane_state->crtc_h, in drm_atomic_plane_check()
1271 plane_state->crtc_w = 0; in __drm_atomic_helper_disable_plane()
1405 primary_state->crtc_w = hdisplay; in __drm_atomic_helper_set_config()
/drivers/gpu/drm/selftests/
Dtest-drm_plane_helper.c52 unsigned crtc_w, unsigned crtc_h) in set_crtc() argument
56 plane_state->crtc_w = crtc_w; in set_crtc()
62 unsigned crtc_w, unsigned crtc_h) in check_crtc_eq() argument
66 drm_rect_width(&plane_state->dst) != crtc_w || in check_crtc_eq()
/drivers/gpu/drm/shmobile/
Dshmob_drm_plane.c33 unsigned int crtc_w; member
133 (splane->crtc_w << LDBBSSZR_BHSS_SHIFT)); in __shmob_drm_plane_setup()
172 unsigned int crtc_w, unsigned int crtc_h, in shmob_drm_plane_update() argument
188 if (src_w >> 16 != crtc_w || src_h >> 16 != crtc_h) { in shmob_drm_plane_update()
199 splane->crtc_w = crtc_w; in shmob_drm_plane_update()
/drivers/gpu/drm/vc4/
Dvc4_plane.c294 vc4_pstate->crtc_w = DIV_ROUND_CLOSEST(vc4_pstate->crtc_w * in vc4_plane_margins_adj()
301 if (!vc4_pstate->crtc_w || !vc4_pstate->crtc_h) in vc4_plane_margins_adj()
349 vc4_state->crtc_w = state->dst.x2 - state->dst.x1; in vc4_plane_setup_clipping_and_scaling()
357 vc4_state->crtc_w); in vc4_plane_setup_clipping_and_scaling()
372 vc4_state->crtc_w); in vc4_plane_setup_clipping_and_scaling()
428 u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w); in vc4_lbm_size()
464 vc4_state->src_w[channel], vc4_state->crtc_w); in vc4_write_scaling_parameters()
477 vc4_state->src_w[channel], vc4_state->crtc_w); in vc4_write_scaling_parameters()
535 vc4_state->hvs_load += vc4_state->crtc_h * vc4_state->crtc_w; in vc4_plane_calc_load()
802 VC4_SET_FIELD(vc4_state->crtc_w, in vc4_plane_mode_set()
[all …]
/drivers/gpu/drm/exynos/
Dexynos_drm_plane.c63 unsigned int crtc_w, crtc_h; in exynos_plane_mode_set() local
77 crtc_w = state->crtc_w; in exynos_plane_mode_set()
86 exynos_state->h_ratio = (src_w << 16) / crtc_w; in exynos_plane_mode_set()
90 actual_w = exynos_plane_get_size(crtc_x, crtc_w, mode->hdisplay); in exynos_plane_mode_set()
/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_plane.c317 if (((state->src_w >> 16) != state->crtc_w) || in mdp5_plane_atomic_check_with_state()
466 plane->state->crtc_w != state->crtc_w || in mdp5_plane_atomic_async_check()
824 unsigned int crtc_w, unsigned int crtc_h, in mdp5_hwpipe_mode_set() argument
847 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) | in mdp5_hwpipe_mode_set()
931 unsigned int crtc_w, crtc_h; in mdp5_plane_mode_set() local
953 crtc_w = drm_rect_width(dest); in mdp5_plane_mode_set()
967 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); in mdp5_plane_mode_set()
976 crtc_w /= 2; in mdp5_plane_mode_set()
981 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x); in mdp5_plane_mode_set()
990 calc_pixel_ext(format, src_w, crtc_w, step.x, in mdp5_plane_mode_set()
[all …]
/drivers/gpu/drm/atmel-hlcdc/
Datmel_hlcdc_plane.c48 unsigned int crtc_w; member
292 if (state->crtc_w == state->src_w && state->crtc_h == state->src_h) { in atmel_hlcdc_plane_setup_scaler()
300 state->crtc_w, in atmel_hlcdc_plane_setup_scaler()
308 state->crtc_w < state->src_w ? in atmel_hlcdc_plane_setup_scaler()
321 xfactor = (1024 * state->src_w) / state->crtc_w; in atmel_hlcdc_plane_setup_scaler()
339 ATMEL_HLCDC_LAYER_SIZE(state->crtc_w, in atmel_hlcdc_plane_update_pos_and_size()
558 if (ovl_state->crtc_h * ovl_state->crtc_w < disc_h * disc_w) in atmel_hlcdc_plane_prepare_disc_area()
564 disc_w = ovl_state->crtc_w; in atmel_hlcdc_plane_prepare_disc_area()
626 state->crtc_w = drm_rect_width(&s->dst); in atmel_hlcdc_plane_atomic_check()
703 (mode->hdisplay != state->crtc_w || in atmel_hlcdc_plane_atomic_check()
[all …]
/drivers/gpu/drm/i915/display/
Dintel_sprite.c370 u32 crtc_w = drm_rect_width(&plane_state->base.dst); in skl_program_scaler() local
408 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h); in skl_program_scaler()
943 u32 crtc_w = drm_rect_width(&plane_state->base.dst); in vlv_update_plane() local
953 crtc_w--; in vlv_update_plane()
963 I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w); in vlv_update_plane()
1159 u32 crtc_w = drm_rect_width(&plane_state->base.dst); in ivb_update_plane() local
1173 crtc_w--; in ivb_update_plane()
1176 if (crtc_w != src_w || crtc_h != src_h) in ivb_update_plane()
1185 I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); in ivb_update_plane()
1412 u32 crtc_w = drm_rect_width(&plane_state->base.dst); in g4x_update_plane() local
[all …]
/drivers/gpu/drm/tilcdc/
Dtilcdc_plane.c48 if (crtc_state->mode.hdisplay != state->crtc_w || in tilcdc_plane_atomic_check()
53 state->crtc_w, state->crtc_h); in tilcdc_plane_atomic_check()
/drivers/gpu/drm/sun4i/
Dsun4i_frontend.c504 state->crtc_w, state->crtc_h); in sun4i_frontend_update_coord()
518 SUN4I_FRONTEND_OUTSIZE(state->crtc_h, state->crtc_w)); in sun4i_frontend_update_coord()
520 SUN4I_FRONTEND_OUTSIZE(state->crtc_h, state->crtc_w)); in sun4i_frontend_update_coord()
523 (luma_width << 16) / state->crtc_w); in sun4i_frontend_update_coord()
525 (chroma_width << 16) / state->crtc_w); in sun4i_frontend_update_coord()
Dsun4i_backend.c176 state->crtc_w, state->crtc_h); in sun4i_backend_update_layer_coord()
178 SUN4I_BACKEND_DISSIZE(state->crtc_w, in sun4i_backend_update_layer_coord()
184 state->crtc_w, state->crtc_h); in sun4i_backend_update_layer_coord()
186 SUN4I_BACKEND_LAYSIZE(state->crtc_w, in sun4i_backend_update_layer_coord()
416 src_w, src_h, state->crtc_w, state->crtc_h); in sun4i_backend_plane_uses_scaler()
418 if ((state->crtc_h != src_h) || (state->crtc_w != src_w)) in sun4i_backend_plane_uses_scaler()
/drivers/gpu/drm/hisilicon/kirin/
Dkirin_drm_ade.c730 int crtc_y, unsigned int crtc_w, in ade_update_channel() argument
743 crtc_x, crtc_y, crtc_w, crtc_h); in ade_update_channel()
791 u32 crtc_w = state->crtc_w; in ade_plane_atomic_check() local
806 if (src_w != crtc_w || src_h != crtc_h) { in ade_plane_atomic_check()
817 if (crtc_x + crtc_w > crtc_state->adjusted_mode.hdisplay || in ade_plane_atomic_check()
831 state->crtc_w, state->crtc_h, in ade_plane_atomic_update()
Dkirin_drm_dpe.c923 int crtc_y, unsigned int crtc_w, in dpe_update_channel() argument
976 state->crtc_w, state->crtc_h, in dpe_plane_atomic_update()
993 u32 crtc_w = state->crtc_w; in dpe_plane_atomic_check() local
1008 if (src_w != crtc_w || src_h != crtc_h) { in dpe_plane_atomic_check()
1020 if (crtc_x + crtc_w > crtc_state->adjusted_mode.hdisplay || in dpe_plane_atomic_check()
/drivers/gpu/drm/imx/
Dipuv3-plane.h40 unsigned int crtc_w, unsigned int crtc_h,
/drivers/gpu/drm/arm/
Dmalidp_planes.c297 if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) { in malidp_se_check_scaling()
549 if ((state->crtc_w > mp->hwdev->max_line_size) || in malidp_de_plane_check()
551 (state->crtc_w < mp->hwdev->min_line_size) || in malidp_de_plane_check()
594 val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_w, in malidp_de_plane_check()
818 dest_w = state->crtc_w; in malidp_de_plane_update()
Dmalidp_crtc.c282 h_upscale_factor = div_u64((u64)pstate->crtc_w << 32, in malidp_crtc_atomic_check_scaling()
298 s->output_w = pstate->crtc_w; in malidp_crtc_atomic_check_scaling()
/drivers/gpu/drm/virtio/
Dvirtgpu_plane.c170 plane->state->crtc_w, plane->state->crtc_h, in virtio_gpu_primary_plane_update()
256 cpu_to_le32(plane->state->crtc_w), in virtio_gpu_cursor_plane_update()
/drivers/gpu/drm/sti/
Dsti_gdp.c639 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); in sti_gdp_atomic_check()
723 (oldstate->crtc_w == state->crtc_w) && in sti_gdp_atomic_update()
748 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); in sti_gdp_atomic_update()
/drivers/gpu/drm/hisilicon/hibmc/
Dhibmc_drm_de.c73 if (src_w != state->crtc_w || src_h != state->crtc_h) { in hibmc_plane_atomic_check()
83 if (state->crtc_x + state->crtc_w > in hibmc_plane_atomic_check()

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