| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clock_source.c | 52 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
831 if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE) in dce112_program_pixel_clk_resync()
1317 const struct dce110_clk_src_mask *cs_mask) in dce110_clk_src_construct() argument
1329 clk_src->cs_mask = cs_mask; in dce110_clk_src_construct()
1342 clk_src->cs_mask->PLL_POST_DIV_PIXCLK; in dce110_clk_src_construct()
1344 calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; in dce110_clk_src_construct()
1361 clk_src->cs_mask->PLL_POST_DIV_PIXCLK; in dce110_clk_src_construct()
1363 calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; in dce110_clk_src_construct()
1417 const struct dce110_clk_src_mask *cs_mask) in dce112_clk_src_construct() argument
1426 clk_src->cs_mask = cs_mask; in dce112_clk_src_construct()
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| D | dce_clock_source.h | 166 const struct dce110_clk_src_mask *cs_mask; member
193 const struct dce110_clk_src_mask *cs_mask);
202 const struct dce110_clk_src_mask *cs_mask);
212 const struct dce110_clk_src_mask *cs_mask);
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| /drivers/spi/ |
| D | spi-dln2.c | 131 static int dln2_spi_cs_set(struct dln2_spi *dln2, u8 cs_mask) in dln2_spi_cs_set() argument
145 tx.cs = ~cs_mask; in dln2_spi_cs_set()
161 static int dln2_spi_cs_enable(struct dln2_spi *dln2, u8 cs_mask, bool enable) in dln2_spi_cs_enable() argument
170 tx.cs = cs_mask; in dln2_spi_cs_enable()
178 u8 cs_mask = GENMASK(dln2->master->num_chipselect - 1, 0); in dln2_spi_cs_enable_all() local
180 return dln2_spi_cs_enable(dln2, cs_mask, enable); in dln2_spi_cs_enable_all()
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| /drivers/usb/host/ |
| D | ehci-sched.c | 203 ps->usecs, ps->c_usecs, ps->cs_mask); in bandwidth_dbg()
239 if (qh->ps.cs_mask & m) in reserve_release_intr_bandwidth()
904 qh->ps.cs_mask = qh->ps.period ? in qh_schedule()
910 hw->hw_info2 |= cpu_to_hc32(ehci, qh->ps.cs_mask); in qh_schedule()
1106 stream->ps.cs_mask = 1; in iso_stream_init()
1110 stream->ps.cs_mask |= tmp << (8 + 2); in iso_stream_init()
1112 stream->ps.cs_mask = smask_out[hs_transfers - 1]; in iso_stream_init()
1345 s_mask = stream->ps.cs_mask; in reserve_release_iso_bandwidth()
1404 mask = stream->ps.cs_mask << (uframe & 7); in sitd_slot_ok()
1407 if (((stream->ps.cs_mask & 0xff) << (uframe & 7)) >= (1 << 7)) in sitd_slot_ok()
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| D | ehci.h | 53 u16 cs_mask; /* C-mask and S-mask bytes */ member
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| D | ehci-dbg.c | 583 ps->bw_period, ps->cs_mask); in fill_bandwidth_buffer()
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| /drivers/edac/ |
| D | amd64_edac.c | 1829 u64 cs_base, cs_mask; in f1x_lookup_addr_in_dct() local
1845 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); in f1x_lookup_addr_in_dct()
1848 csrow, cs_base, cs_mask); in f1x_lookup_addr_in_dct()
1850 cs_mask = ~cs_mask; in f1x_lookup_addr_in_dct()
1853 (in_addr & cs_mask), (cs_base & cs_mask)); in f1x_lookup_addr_in_dct()
1855 if ((in_addr & cs_mask) == (cs_base & cs_mask)) { in f1x_lookup_addr_in_dct()
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| /drivers/pcmcia/ |
| D | tcic.c | 463 u_int cs_mask = mask & ((cs_irq) ? (1<<cs_irq) : ~(1<<12)); in init_tcic() local
465 if ((cs_mask & (1 << i)) && in init_tcic()
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| D | i82365.c | 706 u_int cs_mask = mask & ((cs_irq) ? (1<<cs_irq) : ~(1<<12)); in add_pcic() local
708 if ((cs_mask & (1 << cs_irq)) && in add_pcic()
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| /drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.c | 326 static const struct dce110_clk_src_mask cs_mask = { variable
666 regs, &cs_shift, &cs_mask)) { in dce100_clock_source_create()
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| /drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_resource.c | 377 static const struct dce110_clk_src_mask cs_mask = { variable
498 regs, &cs_shift, &cs_mask)) { in dce120_clock_source_create()
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| /drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_resource.c | 362 static const struct dce110_clk_src_mask cs_mask = { variable
685 regs, &cs_shift, &cs_mask)) { in dce112_clock_source_create()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 356 static const struct dce110_clk_src_mask cs_mask = { variable
712 regs, &cs_shift, &cs_mask)) { in dce110_clock_source_create()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.c | 490 static const struct dce110_clk_src_mask cs_mask = { variable
784 regs, &cs_shift, &cs_mask)) { in dcn10_clock_source_create()
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| /drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_resource.c | 345 static const struct dce110_clk_src_mask cs_mask = { variable
699 regs, &cs_shift, &cs_mask)) { in dce80_clock_source_create()
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 344 static const struct dce110_clk_src_mask cs_mask = { variable
1134 regs, &cs_shift, &cs_mask)) { in dcn21_clock_source_create()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 377 static const struct dce110_clk_src_mask cs_mask = { variable
1075 regs, &cs_shift, &cs_mask)) { in dcn20_clock_source_create()
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