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Searched refs:ctrl1 (Results 1 – 25 of 44) sorted by relevance

12

/drivers/gpu/drm/tve200/
Dtve200_display.c132 u32 ctrl1 = 0; in tve200_display_enable() local
137 ctrl1 |= TVE200_CTRL_CSMODE; in tve200_display_enable()
139 ctrl1 |= TVE200_CTRL_NONINTERLACE; in tve200_display_enable()
141 ctrl1 |= TVE200_CTRL_BURST_32_WORDS; in tve200_display_enable()
143 ctrl1 |= TVE200_CTRL_RETRYCNT_16; in tve200_display_enable()
145 ctrl1 |= TVE200_CTRL_NTSC; in tve200_display_enable()
148 ctrl1 |= TVE200_VSTSTYPE_VSYNC; in tve200_display_enable()
152 ctrl1 |= TVE200_CTRL_TVCLKP; in tve200_display_enable()
156 ctrl1 |= TVE200_CTRL_IPRESOL_CIF; in tve200_display_enable()
159 ctrl1 |= TVE200_CTRL_IPRESOL_VGA; in tve200_display_enable()
[all …]
/drivers/crypto/bcm/
Dspu2.c368 static void spu2_dump_fmd_ctrl1(u64 ctrl1) in spu2_dump_fmd_ctrl1() argument
378 packet_log(" FMD CTRL1 %#16llx\n", ctrl1); in spu2_dump_fmd_ctrl1()
379 if (ctrl1 & SPU2_TAG_LOC) in spu2_dump_fmd_ctrl1()
383 if (ctrl1 & SPU2_HAS_FR_DATA) in spu2_dump_fmd_ctrl1()
385 if (ctrl1 & SPU2_HAS_AAD1) in spu2_dump_fmd_ctrl1()
387 if (ctrl1 & SPU2_HAS_NAAD) in spu2_dump_fmd_ctrl1()
389 if (ctrl1 & SPU2_HAS_AAD2) in spu2_dump_fmd_ctrl1()
391 if (ctrl1 & SPU2_HAS_ESN) in spu2_dump_fmd_ctrl1()
395 hash_key_len = (ctrl1 & SPU2_HASH_KEY_LEN) >> SPU2_HASH_KEY_LEN_SHIFT; in spu2_dump_fmd_ctrl1()
398 ciph_key_len = (ctrl1 & SPU2_CIPH_KEY_LEN) >> SPU2_CIPH_KEY_LEN_SHIFT; in spu2_dump_fmd_ctrl1()
[all …]
/drivers/gpu/drm/aspeed/
Daspeed_gfx_crtc.c31 u32 ctrl1; in aspeed_gfx_set_pixel_fmt() local
33 ctrl1 = readl(priv->base + CRT_CTRL1); in aspeed_gfx_set_pixel_fmt()
34 ctrl1 &= ~CRT_CTRL_COLOR_MASK; in aspeed_gfx_set_pixel_fmt()
39 ctrl1 |= CRT_CTRL_COLOR_RGB565; in aspeed_gfx_set_pixel_fmt()
44 ctrl1 |= CRT_CTRL_COLOR_XRGB8888; in aspeed_gfx_set_pixel_fmt()
52 writel(ctrl1, priv->base + CRT_CTRL1); in aspeed_gfx_set_pixel_fmt()
59 u32 ctrl1 = readl(priv->base + CRT_CTRL1); in aspeed_gfx_enable_controller() local
65 writel(ctrl1 | CRT_CTRL_EN, priv->base + CRT_CTRL1); in aspeed_gfx_enable_controller()
71 u32 ctrl1 = readl(priv->base + CRT_CTRL1); in aspeed_gfx_disable_controller() local
74 writel(ctrl1 & ~CRT_CTRL_EN, priv->base + CRT_CTRL1); in aspeed_gfx_disable_controller()
[all …]
/drivers/rtc/
Drtc-rx8025.c72 u8 ctrl1; member
168 rx8025->ctrl1 & ~RX8025_BIT_CTRL1_DALE)) in rx8025_handle_irq()
197 if (rx8025->ctrl1 & RX8025_BIT_CTRL1_1224) in rx8025_get_time()
227 if (rx8025->ctrl1 & RX8025_BIT_CTRL1_1224) in rx8025_set_time()
259 rx8025->ctrl1 = ctrl[0] & ~RX8025_BIT_CTRL1_TEST; in rx8025_init_client()
305 if (rx8025->ctrl1 & RX8025_BIT_CTRL1_1224) in rx8025_read_alarm()
312 t->enabled = !!(rx8025->ctrl1 & RX8025_BIT_CTRL1_DALE); in rx8025_read_alarm()
340 if (rx8025->ctrl1 & RX8025_BIT_CTRL1_1224) in rx8025_set_alarm()
348 if (rx8025->ctrl1 & RX8025_BIT_CTRL1_DALE) { in rx8025_set_alarm()
349 rx8025->ctrl1 &= ~RX8025_BIT_CTRL1_DALE; in rx8025_set_alarm()
[all …]
Drtc-rv3028.c458 u32 status, ctrl1; in rv3028_eeprom_write() local
462 ret = regmap_read(priv, RV3028_CTRL1, &ctrl1); in rv3028_eeprom_write()
466 if (!(ctrl1 & RV3028_CTRL1_EERD)) { in rv3028_eeprom_write()
509 if (!(ctrl1 & RV3028_CTRL1_EERD)) in rv3028_eeprom_write()
523 u32 status, ctrl1, data; in rv3028_eeprom_read() local
527 ret = regmap_read(priv, RV3028_CTRL1, &ctrl1); in rv3028_eeprom_read()
531 if (!(ctrl1 & RV3028_CTRL1_EERD)) { in rv3028_eeprom_read()
573 if (!(ctrl1 & RV3028_CTRL1_EERD)) in rv3028_eeprom_read()
/drivers/net/can/cc770/
Dcc770.c148 cc770_write_reg(priv, msgobj[mo].ctrl1, in enable_all_objs()
152 cc770_write_reg(priv, msgobj[mo].ctrl1, in enable_all_objs()
159 cc770_write_reg(priv, msgobj[mo].ctrl1, in enable_all_objs()
180 cc770_write_reg(priv, msgobj[mo].ctrl1, in disable_all_objs()
188 cc770_write_reg(priv, msgobj[mo].ctrl1, in disable_all_objs()
269 cc770_write_reg(priv, msgobj[mo].ctrl1, in chipset_init()
399 cc770_write_reg(priv, msgobj[mo].ctrl1, in cc770_tx()
420 cc770_write_reg(priv, msgobj[mo].ctrl1, in cc770_tx()
437 msgobj[mo].ctrl1) & TXRQST_UNC) == TXRQST_SET) { in cc770_start_xmit()
448 static void cc770_rx(struct net_device *dev, unsigned int mo, u8 ctrl1) in cc770_rx() argument
[all …]
/drivers/net/phy/
Dphy-c45.c17 int ctrl1, ctrl2, ret; in genphy_c45_pma_setup_forced() local
23 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_pma_setup_forced()
24 if (ctrl1 < 0) in genphy_c45_pma_setup_forced()
25 return ctrl1; in genphy_c45_pma_setup_forced()
31 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL; in genphy_c45_pma_setup_forced()
43 ctrl1 |= MDIO_PMA_CTRL1_SPEED100; in genphy_c45_pma_setup_forced()
47 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000; in genphy_c45_pma_setup_forced()
52 ctrl1 |= MDIO_CTRL1_SPEED2_5G; in genphy_c45_pma_setup_forced()
57 ctrl1 |= MDIO_CTRL1_SPEED5G; in genphy_c45_pma_setup_forced()
62 ctrl1 |= MDIO_CTRL1_SPEED10G; in genphy_c45_pma_setup_forced()
[all …]
/drivers/spi/
Dspi-mpc52xx.c147 u8 ctrl1; in mpc52xx_spi_fsmstate_idle() local
162 ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR; in mpc52xx_spi_fsmstate_idle()
165 ctrl1 |= SPI_CTRL1_CPHA; in mpc52xx_spi_fsmstate_idle()
167 ctrl1 |= SPI_CTRL1_CPOL; in mpc52xx_spi_fsmstate_idle()
169 ctrl1 |= SPI_CTRL1_LSBFE; in mpc52xx_spi_fsmstate_idle()
170 out_8(ms->regs + SPI_CTRL1, ctrl1); in mpc52xx_spi_fsmstate_idle()
384 u8 ctrl1; in mpc52xx_spi_probe() local
395 ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR; in mpc52xx_spi_probe()
396 out_8(regs + SPI_CTRL1, ctrl1); in mpc52xx_spi_probe()
406 out_8(regs + SPI_CTRL1, ctrl1); in mpc52xx_spi_probe()
/drivers/gpu/drm/mxsfb/
Dmxsfb_crtc.c51 u32 ctrl, ctrl1; in mxsfb_set_pixel_fmt() local
63 ctrl1 = readl(mxsfb->base + LCDC_CTRL1); in mxsfb_set_pixel_fmt()
64 ctrl1 &= CTRL1_CUR_FRAME_DONE_IRQ_EN | CTRL1_CUR_FRAME_DONE_IRQ; in mxsfb_set_pixel_fmt()
70 ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0xf); in mxsfb_set_pixel_fmt()
76 ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0x7); in mxsfb_set_pixel_fmt()
83 writel(ctrl1, mxsfb->base + LCDC_CTRL1); in mxsfb_set_pixel_fmt()
/drivers/usb/host/
Dsl811-hcd.c94 sl811->ctrl1 = 0; in port_power()
114 sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1); in port_power()
689 sl811->ctrl1 = 0; in sl811h_irq()
690 sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1); in sl811h_irq()
868 if (!(sl811->ctrl1 & SL11H_CTL1MASK_LSPD)) in sl811h_urb_enqueue()
1127 u8 signaling = sl811->ctrl1 & SL11H_CTL1MASK_FORCE; in sl811h_timer()
1135 sl811->ctrl1 &= ~SL11H_CTL1MASK_FORCE; in sl811h_timer()
1136 sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1); in sl811h_timer()
1146 sl811->ctrl1 = 0; in sl811h_timer()
1184 sl811->ctrl1 |= SL11H_CTL1MASK_LSPD; in sl811h_timer()
[all …]
/drivers/leds/
Dleds-is31fl319x.c116 u8 ctrl1 = 0, ctrl2 = 0; in is31fl319x_brightness_set() local
143 ctrl1 |= on << i; /* 0..2 => bit 0..2 */ in is31fl319x_brightness_set()
145 ctrl1 |= on << (i + 1); /* 3..5 => bit 4..6 */ in is31fl319x_brightness_set()
150 if (ctrl1 > 0 || ctrl2 > 0) { in is31fl319x_brightness_set()
152 ctrl1, ctrl2); in is31fl319x_brightness_set()
153 regmap_write(is31->regmap, IS31FL319X_CTRL1, ctrl1); in is31fl319x_brightness_set()
/drivers/staging/comedi/drivers/
Dme_daq.c139 unsigned short ctrl1; /* Mirror of CONTROL_1 register */ member
269 devpriv->ctrl1 |= ME_CTRL1_ADC_MODE_SOFT_TRIG; in me_ai_insn_read()
270 writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG); in me_ai_insn_read()
289 devpriv->ctrl1 &= ~ME_CTRL1_ADC_MODE_MASK; in me_ai_insn_read()
290 writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG); in me_ai_insn_read()
421 devpriv->ctrl1 = 0; in me_reset()
/drivers/staging/ralink-gdma/
Dralink-gdma.c275 u32 ctrl0, ctrl1; in rt305x_gdma_start_transfer() local
318 ctrl1 = chan->id << GDMA_REG_CTRL1_NEXT_SHIFT; in rt305x_gdma_start_transfer()
323 gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1); in rt305x_gdma_start_transfer()
352 u32 ctrl0, ctrl1; in rt3883_gdma_start_transfer() local
368 ctrl1 = (32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) | in rt3883_gdma_start_transfer()
374 ctrl1 = (chan->slave_id << GDMA_REG_CTRL1_SRC_REQ_SHIFT) | in rt3883_gdma_start_transfer()
381 ctrl1 = (32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) | in rt3883_gdma_start_transfer()
393 ctrl1 |= chan->id << GDMA_REG_CTRL1_NEXT_SHIFT; in rt3883_gdma_start_transfer()
398 gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1); in rt3883_gdma_start_transfer()
/drivers/thermal/
Darmada_thermal.c503 u32 ctrl1; in armada_set_overheat_thresholds() local
505 regmap_read(priv->syscon, data->syscon_control1_off, &ctrl1); in armada_set_overheat_thresholds()
509 ctrl1 &= ~(data->temp_mask << data->thresh_shift); in armada_set_overheat_thresholds()
510 ctrl1 |= threshold << data->thresh_shift; in armada_set_overheat_thresholds()
516 ctrl1 &= ~(data->hyst_mask << data->hyst_shift); in armada_set_overheat_thresholds()
517 ctrl1 |= hysteresis << data->hyst_shift; in armada_set_overheat_thresholds()
521 regmap_write(priv->syscon, data->syscon_control1_off, ctrl1); in armada_set_overheat_thresholds()
/drivers/extcon/
Dextcon-max8997.c198 u8 ctrl1, ctrl2 = 0; in max8997_muic_set_path() local
201 ctrl1 = val; in max8997_muic_set_path()
203 ctrl1 = CONTROL1_SW_OPEN; in max8997_muic_set_path()
206 MAX8997_MUIC_REG_CONTROL1, ctrl1, COMP_SW_MASK); in max8997_muic_set_path()
227 ctrl1, ctrl2, attached ? "attached" : "detached"); in max8997_muic_set_path()
Dextcon-max14577.c197 u8 ctrl1, ctrl2 = 0; in max14577_muic_set_path() local
210 ctrl1 = val; in max14577_muic_set_path()
212 ctrl1 = CTRL1_SW_OPEN; in max14577_muic_set_path()
216 CLEAR_IDBEN_MICEN_MASK, ctrl1); in max14577_muic_set_path()
237 ctrl1, ctrl2, attached ? "attached" : "detached"); in max14577_muic_set_path()
Dextcon-max77843.c204 unsigned int ctrl1, ctrl2; in max77843_muic_set_path() local
207 ctrl1 = val; in max77843_muic_set_path()
209 ctrl1 = MAX77843_MUIC_CONTROL1_SW_OPEN; in max77843_muic_set_path()
212 ctrl1 |= MAX77843_MUIC_CONTROL1_NOBCCOMP_MASK; in max77843_muic_set_path()
219 ctrl1); in max77843_muic_set_path()
241 ctrl1, ctrl2, attached ? "attached" : "detached"); in max77843_muic_set_path()
Dextcon-max77693.c260 unsigned int ctrl1, ctrl2 = 0; in max77693_muic_set_path() local
263 ctrl1 = val; in max77693_muic_set_path()
265 ctrl1 = MAX77693_CONTROL1_SW_OPEN; in max77693_muic_set_path()
268 MAX77693_MUIC_REG_CTRL1, COMP_SW_MASK, ctrl1); in max77693_muic_set_path()
290 ctrl1, ctrl2, attached ? "attached" : "detached"); in max77693_muic_set_path()
/drivers/pinctrl/intel/
Dpinctrl-cherryview.c724 u32 ctrl0, ctrl1; in chv_pin_dbg_show() local
730 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1)); in chv_pin_dbg_show()
746 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1); in chv_pin_dbg_show()
974 u32 ctrl0, ctrl1; in chv_config_get() local
980 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); in chv_config_get()
1025 if (!(ctrl1 & CHV_PADCTRL1_ODEN)) in chv_config_get()
1119 u32 ctrl1; in chv_config_set_oden() local
1122 ctrl1 = readl(reg); in chv_config_set_oden()
1125 ctrl1 |= CHV_PADCTRL1_ODEN; in chv_config_set_oden()
1127 ctrl1 &= ~CHV_PADCTRL1_ODEN; in chv_config_set_oden()
[all …]
/drivers/usb/cdns3/
Ddrd.h37 __le32 ctrl1; member
57 __le32 ctrl1; member
/drivers/media/i2c/
Dov2659.c205 u8 ctrl1; member
738 static const struct pll_ctrl_reg ctrl1[] = { variable
921 for (i = 0; ctrl1[i].div != 0; i++) { in ov2659_pll_calc_params()
922 postdiv = ctrl1[i].div; in ov2659_pll_calc_params()
935 ctrl1_reg = ctrl1[i].reg; in ov2659_pll_calc_params()
943 ov2659->pll.ctrl1 = ctrl1_reg; in ov2659_pll_calc_params()
956 {REG_SC_PLL_CTRL1, ov2659->pll.ctrl1}, in ov2659_set_pixel_clock()
/drivers/net/wireless/ath/ath9k/
Dar9003_paprd.c146 static const u32 ctrl1[3] = { in ar9003_paprd_setup_single_table() local
186 REG_RMW_FIELD(ah, ctrl1[i], in ar9003_paprd_setup_single_table()
188 REG_RMW_FIELD(ah, ctrl1[i], in ar9003_paprd_setup_single_table()
190 REG_RMW_FIELD(ah, ctrl1[i], in ar9003_paprd_setup_single_table()
192 REG_RMW_FIELD(ah, ctrl1[i], in ar9003_paprd_setup_single_table()
194 REG_RMW_FIELD(ah, ctrl1[i], in ar9003_paprd_setup_single_table()
196 REG_RMW_FIELD(ah, ctrl1[i], in ar9003_paprd_setup_single_table()
/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.c995 val |= pll->state.hw_state.ctrl1 << (id * 6); in skl_ddi_pll_write_ctrl1()
1067 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; in skl_ddi_pll_get_hw_state()
1105 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; in skl_ddi_dpll0_get_hw_state()
1363 u32 ctrl1, cfgcr1, cfgcr2; in skl_ddi_hdmi_pll_dividers() local
1370 ctrl1 = DPLL_CTRL1_OVERRIDE(0); in skl_ddi_hdmi_pll_dividers()
1372 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); in skl_ddi_hdmi_pll_dividers()
1391 crtc_state->dpll_hw_state.ctrl1 = ctrl1; in skl_ddi_hdmi_pll_dividers()
1400 u32 ctrl1; in skl_ddi_dp_set_dpll_hw_state() local
1406 ctrl1 = DPLL_CTRL1_OVERRIDE(0); in skl_ddi_dp_set_dpll_hw_state()
1409 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); in skl_ddi_dp_set_dpll_hw_state()
[all …]
/drivers/net/ethernet/neterion/vxge/
Dvxge-config.h1425 #define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(ctrl1) vxge_bVALn(ctrl1, 2, 14) argument
1429 #define VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET(ctrl1) vxge_bVALn(ctrl1, 16, 32) argument
1431 #define VXGE_HW_RING_RXD_VLAN_TAG_GET(ctrl1) vxge_bVALn(ctrl1, 48, 16) argument
/drivers/net/ethernet/huawei/hinic/
Dhinic_hw_eqs.c472 u32 addr, val, ctrl1; in set_ctrl1() local
487 ctrl1 = HINIC_AEQ_CTRL_1_SET(eq->q_len, LEN) | in set_ctrl1()
491 val |= ctrl1; in set_ctrl1()
505 ctrl1 = HINIC_CEQ_CTRL_1_SET(eq->q_len, LEN) | in set_ctrl1()
508 val |= ctrl1; in set_ctrl1()

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