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Searched refs:ctrl2 (Results 1 – 25 of 28) sorted by relevance

12

/drivers/rtc/
Drtc-rx8025.c107 int ctrl2; in rx8025_check_validity() local
109 ctrl2 = rx8025_read_reg(rx8025->client, RX8025_REG_CTRL2); in rx8025_check_validity()
110 if (ctrl2 < 0) in rx8025_check_validity()
111 return ctrl2; in rx8025_check_validity()
113 if (ctrl2 & RX8025_BIT_CTRL2_VDET) in rx8025_check_validity()
116 if (ctrl2 & RX8025_BIT_CTRL2_PON) { in rx8025_check_validity()
121 if (!(ctrl2 & RX8025_BIT_CTRL2_XST)) { in rx8025_check_validity()
131 int ctrl2 = rx8025_read_reg(client, RX8025_REG_CTRL2); in rx8025_reset_validity() local
133 if (ctrl2 < 0) in rx8025_reset_validity()
134 return ctrl2; in rx8025_reset_validity()
[all …]
Drtc-rs5c372.c214 unsigned char ctrl2 = rs5c->regs[RS5C_REG_CTRL2]; in rs5c372_rtc_read_time() local
222 if ((rs5c->type == rtc_r2025sd && !(ctrl2 & R2x2x_CTRL2_XSTP)) || in rs5c372_rtc_read_time()
223 (rs5c->type == rtc_r2221tl && (ctrl2 & R2x2x_CTRL2_XSTP))) { in rs5c372_rtc_read_time()
229 if (ctrl2 & RS5C_CTRL2_XSTP) { in rs5c372_rtc_read_time()
262 unsigned char ctrl2; in rs5c372_rtc_set_time() local
287 ctrl2 = i2c_smbus_read_byte_data(client, addr); in rs5c372_rtc_set_time()
293 ctrl2 &= ~(R2x2x_CTRL2_VDET | R2x2x_CTRL2_PON); in rs5c372_rtc_set_time()
295 ctrl2 |= R2x2x_CTRL2_XSTP; in rs5c372_rtc_set_time()
297 ctrl2 &= ~R2x2x_CTRL2_XSTP; in rs5c372_rtc_set_time()
300 ctrl2 &= ~RS5C_CTRL2_XSTP; in rs5c372_rtc_set_time()
[all …]
/drivers/staging/comedi/drivers/
Dme_daq.c140 unsigned short ctrl2; /* Mirror of CONTROL_2 register */ member
169 devpriv->ctrl2 |= ME_CTRL2_PORT_A_ENA; in me_dio_insn_config()
171 devpriv->ctrl2 &= ~ME_CTRL2_PORT_A_ENA; in me_dio_insn_config()
173 devpriv->ctrl2 |= ME_CTRL2_PORT_B_ENA; in me_dio_insn_config()
175 devpriv->ctrl2 &= ~ME_CTRL2_PORT_B_ENA; in me_dio_insn_config()
177 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_dio_insn_config()
251 devpriv->ctrl2 &= ~(ME_CTRL2_ADFIFO_ENA | ME_CTRL2_CHANLIST_ENA); in me_ai_insn_read()
252 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ai_insn_read()
257 devpriv->ctrl2 |= (ME_CTRL2_ADFIFO_ENA | ME_CTRL2_CHANLIST_ENA); in me_ai_insn_read()
258 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ai_insn_read()
[all …]
/drivers/net/phy/
Dphy-c45.c17 int ctrl1, ctrl2, ret; in genphy_c45_pma_setup_forced() local
27 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); in genphy_c45_pma_setup_forced()
28 if (ctrl2 < 0) in genphy_c45_pma_setup_forced()
29 return ctrl2; in genphy_c45_pma_setup_forced()
36 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30); in genphy_c45_pma_setup_forced()
40 ctrl2 |= MDIO_PMA_CTRL2_10BT; in genphy_c45_pma_setup_forced()
44 ctrl2 |= MDIO_PMA_CTRL2_100BTX; in genphy_c45_pma_setup_forced()
49 ctrl2 |= MDIO_PMA_CTRL2_1000BT; in genphy_c45_pma_setup_forced()
54 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT; in genphy_c45_pma_setup_forced()
59 ctrl2 |= MDIO_PMA_CTRL2_5GBT; in genphy_c45_pma_setup_forced()
[all …]
/drivers/pci/
Dvc.c106 u32 ctrl, header, cap1, ctrl2; in pci_vc_enable() local
139 pci_read_config_dword(dev->bus->self, ctrl_pos2, &ctrl2); in pci_vc_enable()
140 if ((ctrl2 & PCI_VC_RES_CTRL_ID) == id) { in pci_vc_enable()
150 if (ctrl2 & PCI_VC_RES_CTRL_ENABLE) { in pci_vc_enable()
151 ctrl2 &= ~PCI_VC_RES_CTRL_ENABLE; in pci_vc_enable()
152 pci_write_config_dword(link, ctrl_pos2, ctrl2); in pci_vc_enable()
156 ctrl2 |= PCI_VC_RES_CTRL_ENABLE; in pci_vc_enable()
157 pci_write_config_dword(link, ctrl_pos2, ctrl2); in pci_vc_enable()
/drivers/mmc/host/
Dsdhci-pci-gli.c108 u16 ctrl2; in gli_set_9750() local
165 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in gli_set_9750()
166 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; in gli_set_9750()
167 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in gli_set_9750()
185 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in gli_set_9750()
186 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; in gli_set_9750()
187 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in gli_set_9750()
Dsdhci.c124 u16 ctrl2; in sdhci_do_enable_v4_mode() local
126 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_do_enable_v4_mode()
127 if (ctrl2 & SDHCI_CTRL_V4_MODE) in sdhci_do_enable_v4_mode()
130 ctrl2 |= SDHCI_CTRL_V4_MODE; in sdhci_do_enable_v4_mode()
131 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in sdhci_do_enable_v4_mode()
272 u16 ctrl2; in sdhci_config_dma() local
299 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_config_dma()
300 ctrl2 |= SDHCI_CTRL_64BIT_ADDR; in sdhci_config_dma()
301 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in sdhci_config_dma()
1157 u16 ctrl2; in sdhci_auto_cmd_select() local
[all …]
/drivers/media/platform/vsp1/
Dvsp1_sru.c41 u32 ctrl2; member
56 .ctrl2 = VI6_SRU_CTRL2_PARAMS(24, 40, 255),
59 .ctrl2 = VI6_SRU_CTRL2_PARAMS(8, 16, 255),
62 .ctrl2 = VI6_SRU_CTRL2_PARAMS(36, 60, 255),
65 .ctrl2 = VI6_SRU_CTRL2_PARAMS(12, 27, 255),
68 .ctrl2 = VI6_SRU_CTRL2_PARAMS(48, 80, 255),
71 .ctrl2 = VI6_SRU_CTRL2_PARAMS(16, 36, 255),
301 vsp1_sru_write(sru, dlb, VI6_SRU_CTRL2, param->ctrl2); in sru_configure_stream()
/drivers/crypto/bcm/
Dspu2.c445 static void spu2_dump_fmd_ctrl2(u64 ctrl2) in spu2_dump_fmd_ctrl2() argument
447 packet_log(" FMD CTRL2 %#16llx\n", ctrl2); in spu2_dump_fmd_ctrl2()
450 ctrl2 & SPU2_AAD1_OFFSET, in spu2_dump_fmd_ctrl2()
451 (ctrl2 & SPU2_AAD1_LEN) >> SPU2_AAD1_LEN_SHIFT); in spu2_dump_fmd_ctrl2()
453 (ctrl2 & SPU2_AAD2_OFFSET) >> SPU2_AAD2_OFFSET_SHIFT); in spu2_dump_fmd_ctrl2()
455 (ctrl2 & SPU2_PL_OFFSET) >> SPU2_PL_OFFSET_SHIFT); in spu2_dump_fmd_ctrl2()
472 spu2_dump_fmd_ctrl2(le64_to_cpu(fmd->ctrl2)); in spu2_dump_fmd()
560 u64 ctrl2; in spu2_fmd_init() local
581 ctrl2 = aad1_offset | in spu2_fmd_init()
590 fmd->ctrl2 = cpu_to_le64(ctrl2); in spu2_fmd_init()
[all …]
Dspu2.h78 u64 ctrl2; member
/drivers/gpu/drm/aspeed/
Daspeed_gfx_crtc.c60 u32 ctrl2 = readl(priv->base + CRT_CTRL2); in aspeed_gfx_enable_controller() local
66 writel(ctrl2 | CRT_CTRL_DAC_EN, priv->base + CRT_CTRL2); in aspeed_gfx_enable_controller()
72 u32 ctrl2 = readl(priv->base + CRT_CTRL2); in aspeed_gfx_disable_controller() local
75 writel(ctrl2 & ~CRT_CTRL_DAC_EN, priv->base + CRT_CTRL2); in aspeed_gfx_disable_controller()
/drivers/leds/
Dleds-is31fl319x.c116 u8 ctrl1 = 0, ctrl2 = 0; in is31fl319x_brightness_set() local
147 ctrl2 |= on << (i - 6); /* 6..8 => bit 0..2 */ in is31fl319x_brightness_set()
150 if (ctrl1 > 0 || ctrl2 > 0) { in is31fl319x_brightness_set()
152 ctrl1, ctrl2); in is31fl319x_brightness_set()
154 regmap_write(is31->regmap, IS31FL319X_CTRL2, ctrl2); in is31fl319x_brightness_set()
/drivers/extcon/
Dextcon-max8997.c198 u8 ctrl1, ctrl2 = 0; in max8997_muic_set_path() local
213 ctrl2 |= CONTROL2_CPEN_MASK; /* LowPwr=0, CPEn=1 */ in max8997_muic_set_path()
215 ctrl2 |= CONTROL2_LOWPWR_MASK; /* LowPwr=1, CPEn=0 */ in max8997_muic_set_path()
218 MAX8997_MUIC_REG_CONTROL2, ctrl2, in max8997_muic_set_path()
227 ctrl1, ctrl2, attached ? "attached" : "detached"); in max8997_muic_set_path()
Dextcon-max14577.c197 u8 ctrl1, ctrl2 = 0; in max14577_muic_set_path() local
223 ctrl2 |= CTRL2_CPEN_MASK; /* LowPwr=0, CPEn=1 */ in max14577_muic_set_path()
225 ctrl2 |= CTRL2_LOWPWR_MASK; /* LowPwr=1, CPEn=0 */ in max14577_muic_set_path()
229 CTRL2_LOWPWR_MASK | CTRL2_CPEN_MASK, ctrl2); in max14577_muic_set_path()
237 ctrl1, ctrl2, attached ? "attached" : "detached"); in max14577_muic_set_path()
Dextcon-max77843.c204 unsigned int ctrl1, ctrl2; in max77843_muic_set_path() local
226 ctrl2 = MAX77843_MUIC_CONTROL2_CPEN_MASK; in max77843_muic_set_path()
228 ctrl2 = MAX77843_MUIC_CONTROL2_LOWPWR_MASK; in max77843_muic_set_path()
233 MAX77843_MUIC_CONTROL2_CPEN_MASK, ctrl2); in max77843_muic_set_path()
241 ctrl1, ctrl2, attached ? "attached" : "detached"); in max77843_muic_set_path()
Dextcon-max77693.c260 unsigned int ctrl1, ctrl2 = 0; in max77693_muic_set_path() local
275 ctrl2 |= MAX77693_CONTROL2_CPEN_MASK; /* LowPwr=0, CPEn=1 */ in max77693_muic_set_path()
277 ctrl2 |= MAX77693_CONTROL2_LOWPWR_MASK; /* LowPwr=1, CPEn=0 */ in max77693_muic_set_path()
282 ctrl2); in max77693_muic_set_path()
290 ctrl1, ctrl2, attached ? "attached" : "detached"); in max77693_muic_set_path()
/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Ddma.c202 __le32 ctrl2; /* buffer count and address extension */ member
303 return parity32(dd->addrlow ^ dd->addrhigh ^ dd->ctrl1 ^ dd->ctrl2); in dma64_dd_parity()
718 u32 ctrl2 = bufcount & D64_CTRL2_BC_MASK; in dma64_dd_upd() local
725 ddring[outidx].ctrl2 = cpu_to_le32(ctrl2); in dma64_dd_upd()
733 ctrl2 |= (ae << D64_CTRL2_AE_SHIFT) & D64_CTRL2_AE; in dma64_dd_upd()
737 ddring[outidx].ctrl2 = cpu_to_le32(ctrl2); in dma64_dd_upd()
741 ddring[outidx].ctrl2 = in dma64_dd_upd()
742 cpu_to_le32(ctrl2 | D64_CTRL2_PARITY); in dma64_dd_upd()
1518 (le32_to_cpu(di->txd64[i].ctrl2) & in dma_getnexttxp()
/drivers/tty/serial/
Dmxs-auart.c979 u32 bm, ctrl, ctrl2, div; in mxs_auart_settermios() local
985 ctrl2 = mxs_read(s, REG_CTRL2); in mxs_auart_settermios()
1043 ctrl2 |= AUART_CTRL2_RXE; in mxs_auart_settermios()
1045 ctrl2 &= ~AUART_CTRL2_RXE; in mxs_auart_settermios()
1052 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN); in mxs_auart_settermios()
1064 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE in mxs_auart_settermios()
1069 ctrl2 |= AUART_CTRL2_RTSEN; in mxs_auart_settermios()
1071 ctrl2 |= AUART_CTRL2_CTSEN; in mxs_auart_settermios()
1092 mxs_write(ctrl2, s, REG_CTRL2); in mxs_auart_settermios()
/drivers/usb/cdns3/
Ddrd.h38 __le32 ctrl2; member
/drivers/usb/host/
Dsl811.h147 u8 ctrl1, ctrl2, irq_enable; member
/drivers/misc/lis3lv02d/
Dlis3lv02d.c885 int ctrl2 = p->hipass_ctrl; in lis3lv02d_8b_configure() local
910 ctrl2 ^= HP_FF_WU1; /* Xor to keep compatible with old pdata*/ in lis3lv02d_8b_configure()
918 ctrl2 ^= HP_FF_WU2; /* Xor to keep compatible with old pdata*/ in lis3lv02d_8b_configure()
921 lis3->write(lis3, CTRL_REG2, ctrl2); in lis3lv02d_8b_configure()
/drivers/net/can/
Dflexcan.c220 u32 ctrl2; /* MX6, VF610 */ member
1140 reg_ctrl2 = priv->read(&regs->ctrl2); in flexcan_chip_start()
1142 priv->write(reg_ctrl2, &regs->ctrl2); in flexcan_chip_start()
1191 reg_ctrl2 = priv->read(&regs->ctrl2); in flexcan_chip_start()
1193 priv->write(reg_ctrl2, &regs->ctrl2); in flexcan_chip_start()
/drivers/media/i2c/
Dov2659.c206 u8 ctrl2; member
944 ov2659->pll.ctrl2 = ctrl2_reg; in ov2659_pll_calc_params()
957 {REG_SC_PLL_CTRL2, ov2659->pll.ctrl2}, in ov2659_set_pixel_clock()
/drivers/gpu/drm/bridge/
Danalogix-anx78xx.c188 u8 ctrl2 = SP_AUX_EN; in anx78xx_aux_transfer() local
198 ctrl2 |= SP_ADDR_ONLY; in anx78xx_aux_transfer()
224 SP_AUX_EN, ctrl2); in anx78xx_aux_transfer()
/drivers/mailbox/
Dbcm-pdc-mailbox.c168 u32 ctrl2; /* buffer count and address extension */ member
533 rxd->ctrl2 = cpu_to_le32(buf_len); in pdc_build_rxd()
561 txd->ctrl2 = cpu_to_le32(buf_len); in pdc_build_txd()

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