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Searched refs:dcfclk_mhz (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr.c347 .dcfclk_mhz = 400,
354 .dcfclk_mhz = 483,
361 .dcfclk_mhz = 602,
368 .dcfclk_mhz = 738,
475 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i].Freq; in clk_mgr_helper_populate_bw_params()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c162 .dcfclk_mhz = 304.0,
173 .dcfclk_mhz = 304.0,
184 .dcfclk_mhz = 608.0,
195 .dcfclk_mhz = 676.0,
206 .dcfclk_mhz = 810.0,
218 .dcfclk_mhz = 810.0,
959 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
1286 dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in update_bw_bounding_box()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c165 .dcfclk_mhz = 560.0,
176 .dcfclk_mhz = 694.0,
187 .dcfclk_mhz = 875.0,
198 .dcfclk_mhz = 1000.0,
209 .dcfclk_mhz = 1200.0,
221 .dcfclk_mhz = 1200.0,
2576 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; in dcn20_calculate_wm()
2582 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz; in dcn20_calculate_wm()
2593 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; in dcn20_calculate_wm()
2604 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; in dcn20_calculate_wm()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_mode_structs.h58 double dcfclk_mhz; member
342 double dcfclk_mhz; member
Ddisplay_mode_vba.c239 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
254 mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
813 mode_lib->vba.DCFCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dcfclk_mhz; in ModeSupportAndSystemConfiguration()
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_socbb.h29 uint32_t dcfclk_mhz; member
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dclk_mgr.h56 unsigned int dcfclk_mhz; member
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c480 input.clks_cfg.dcfclk_mhz = v->dcfclk; in dcn_bw_calc_rq_dlg_ttu()